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Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

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Figures1 Second Level (L2) Cache Implement<strong>at</strong>ion ...........................................................92 AGTL+ Bus Topology..........................................................................................143 S<strong>to</strong>p Clock St<strong>at</strong>e Machine ...................................................................................144 BSEL[1:0] Example <strong>for</strong> a 100 <strong>MHz</strong> System Design (100 <strong>MHz</strong> <strong>Processor</strong>Installed)..............................................................................................................225 BSEL[1:0] Example <strong>for</strong> a 100/133 <strong>MHz</strong> Capable System(100 <strong>MHz</strong> <strong>Processor</strong> Installed) ............................................................................236 BSEL[1:0] Example <strong>for</strong> a 100/133 <strong>MHz</strong> Capable System(133 <strong>MHz</strong> <strong>Processor</strong> Installed) ............................................................................237 BCLK, PICCLK, and TCK Generic Clock Wave<strong>for</strong>m...........................................378 System Bus Valid Delay Timings ........................................................................389 System Bus Setup and Hold Timings..................................................................3810 System Bus Reset and Configur<strong>at</strong>ion Timings....................................................3811 Power-On Reset and Configur<strong>at</strong>ion Timings.......................................................3912 Test Timings (TAP Connection) ..........................................................................3913 Test Reset Timings .............................................................................................3914 BCLK and PICCLK Generic Clock Wave<strong>for</strong>m .....................................................4015 Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/UndershootWave<strong>for</strong>m ............................................................................................................4616 Low <strong>to</strong> High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................4817 Signal Overshoot/Undershoot, Settling Limit, and Ringback...............................4818 S.E.C.Cartridge — 3-Dimensional View..............................................................4919 S.E.C.Cartridge 2 — Substr<strong>at</strong>e View ..................................................................5020 <strong>Processor</strong> Functional Die Layout (CPUID=0686h)..............................................5221 <strong>Processor</strong> Functional Die Layout (up <strong>to</strong> CPUID=0683h).....................................5222 S.E.C.C. Packaged <strong>Processor</strong> — Multiple Views................................................5423 S.E.C.C. Packaged <strong>Processor</strong> — Extended Thermal Pl<strong>at</strong>e SideDimensions..........................................................................................................5524 S.E.C.C. Packaged <strong>Processor</strong> — Bot<strong>to</strong>m View Dimensions...............................5525 S.E.C.C. Packaged <strong>Processor</strong> — L<strong>at</strong>ch Arm, Extended Thermal Pl<strong>at</strong>e Lug,and Cover Lug Dimensions .................................................................................5626 S.E.C.C. Packaged <strong>Processor</strong> — L<strong>at</strong>ch Arm, Extended Thermal Pl<strong>at</strong>e,and Cover Detail Dimensions (Reference Dimensions Only)..............................5727 S.E.C.C. Packaged <strong>Processor</strong> — Extended Thermal Pl<strong>at</strong>e AttachmentDetail Dimensions ...............................................................................................5829 S.E.C.C. Packaged <strong>Processor</strong> Substr<strong>at</strong>e — Edge Finger ContactDimensions..........................................................................................................5928 S.E.C.C. Packaged <strong>Processor</strong> — Extended Thermal Pl<strong>at</strong>e AttachmentDetail Dimensions, Continued .............................................................................5930 S.E.C.C. Packaged <strong>Processor</strong> Substr<strong>at</strong>e — Edge Finger ContactDimensions, Detail A ...........................................................................................6031 <strong>Intel</strong> ® <strong>Pentium</strong>® <strong>III</strong> <strong>Processor</strong> Markings (S.E.C.C. Packaged <strong>Processor</strong>)...........6032 S.E.C.C.2 Packaged <strong>Processor</strong> — Multiple Views..............................................6133 S.E.C.C.2 Packaged <strong>Processor</strong> Assembly — Primary View...............................6234 S.E.C.C.2 Packaged <strong>Processor</strong> Assembly — Cover View with Dimensions ......6235 S.E.C.C.2 Packaged <strong>Processor</strong> Assembly — He<strong>at</strong>sink Attach Boss Section.....6336 S.E.C.C.2 Packaged <strong>Processor</strong> Assembly — Side View ....................................6337 Detail View of Cover in <strong>the</strong> Vicinity of <strong>the</strong> Substr<strong>at</strong>e Attach Fe<strong>at</strong>ures.................6338 S.E.C.C.2 Packaged <strong>Processor</strong> Substr<strong>at</strong>e — Edge Finger ContactDimensions..........................................................................................................64D<strong>at</strong>asheet 5

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