Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

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Intel ® Pentium ® III Processor Signal DescriptionTable 41. Signal Description (Sheet 4 of 7)Name Type DescriptionEMIFERR#FLUSH#HIT#HITM#IERR#IGNNE#INIT#LINT[1:0]IOII/OI/OOIIIEMI pins should be connected to baseboard ground and/or to chassis groundthrough zero ohm (0 Ω) resistors. The 0 Ω resistors should be placed in closeproximity to the processor connector. The path to chassis ground should be short inlength and have a low impedance. These pins are used for EMI managementpurposes.The FERR# (Floating-point Error) signal is asserted when the processor detects anunmasked floating-point error. FERR# is similar to the ERROR# signal on theIntel 387 coprocessor, and is included for compatibility with systems usingMS-DOS*-type floating-point error reporting.When the FLUSH# input signal is asserted, processors write back all data in theModified state from their internal caches and invalidate all internal cache lines. Atthe completion of this operation, the processor issues a Flush Acknowledgetransaction. The processor does not cache any new data while the FLUSH# signalremains asserted.FLUSH# is an asynchronous signal. However, to ensure recognition of this signalfollowing an I/O write instruction, it must be valid along with the TRDY# assertion ofthe corresponding I/O Write bus transaction.On the active-to-inactive transition of RESET#, each processor samples FLUSH#to determine its power-on configuration. See the P6 Family of Processors HardwareDeveloper’s Manual (Document Number 244001) for details.The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoopoperation results, and must connect the appropriate pins of all processor systembus agents. Any such agent may assert both HIT# and HITM# together to indicatethat it requires a snoop stall, which can be continued by reasserting HIT# andHITM# together.The IERR# (Internal Error) signal is asserted by a processor as the result of aninternal error. Assertion of IERR# is usually accompanied by a SHUTDOWNtransaction on the processor system bus. This transaction may optionally beconverted to an external error signal (e.g., NMI) by system core logic. Theprocessor will keep IERR# asserted until the assertion of RESET#, BINIT#, orINIT#.The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor toignore a numeric error and continue to execute noncontrol floating-pointinstructions. If IGNNE# is deasserted, the processor generates an exception on anoncontrol floating-point instruction if a previous floating-point instruction caused anerror. IGNNE# has no effect when the NE bit in control register 0 is set.IGNNE# is an asynchronous signal. However, to ensure recognition of this signalfollowing an I/O write instruction, it must be valid along with the TRDY# assertion ofthe corresponding I/O Write bus transaction.The INIT# (Initialization) signal, when asserted, resets integer registers inside allprocessors without affecting their internal (L1 or L2) caches or floating-pointregisters. Each processor then begins execution at the power-on Reset vectorconfigured during power-on configuration. The processor continues to handlesnoop requests during INIT# assertion. INIT# is an asynchronous signal and mustconnect the appropriate pins of all processor system bus agents.If INIT# is sampled active on the active to inactive transition of RESET#, then theprocessor executes its Built-in Self-Test (BIST).The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins ofall APIC Bus agents, including all processors and the core logic or I/O APICcomponent. When the APIC is disabled, the LINT0 signal becomes INTR, amaskable interrupt request signal, and LINT1 becomes NMI, a nonmaskableinterrupt. INTR and NMI are backward compatible with the signals of those nameson the Pentium processor. Both signals are asynchronous.Both of these signals must be software configured via BIOS programming of theAPIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APICis enabled by default after Reset, operation of these pins as LINT[1:0] is the defaultconfiguration.96 Datasheet
Intel ® Pentium ® III Processor Signal DescriptionTable 41. Signal Description (Sheet 5 of 7)Name Type DescriptionLOCK#PICCLKPICD[1:0]PRDY#PREQ#PWRGOODI/OII/OOIIThe LOCK# signal indicates to the system that a transaction must occur atomically.This signal must connect the appropriate pins of all processor system bus agents.For a locked sequence of transactions, LOCK# is asserted from the beginning ofthe first transaction end of the last transaction.When the priority agent asserts BPRI# to arbitrate for ownership of the processorsystem bus, it will wait until it observes LOCK# deasserted. This enables symmetricagents to retain ownership of the processor system bus throughout the bus lockedoperation and ensure the atomicity of lock.The PICCLK (APIC Clock) signal is an input clock to the processor and core logic orI/O APIC which is required for operation of all processors, core logic, and I/O APICcomponents on the APIC bus.The PICD[1:0] (APIC Data) signals are used for bidirectional serial messagepassing on the APIC bus, and must connect the appropriate pins of all processorsand core logic or I/O APIC components on the APIC bus.The PRDY (Probe Ready) signal is a processor output used by debug tools todetermine processor debug readiness.The PREQ# (Probe Request) signal is used by debug tools to request debugoperation of the processors.The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. Theprocessor requires this signal to be a clean indication that the clocks and powersupplies (VCC CORE , etc.) are stable and within their specifications. Clean impliesthat the signal will remain low (capable of sinking leakage current), without glitches,from the time that the power supplies are turned on until they come withinspecification. The signal must then transition monotonically to a high (2.5 V) state.The figure below illustrates the relationship of PWRGOOD to other system signals.PWRGOOD can be driven inactive at any time, but clocks and power must again bestable before a subsequent rising edge of PWRGOOD. It must also meet theminimum pulse width specification in Table 15, and be followed by a 1 ms RESET#pulse.The PWRGOOD signal must be supplied to the processor; it is used to protectinternal circuits against voltage sequencing issues. It should be driven highthroughout boundary scan operation.PWRGOOD Relationship at Power-OnBCLKV CC,V CCP,V REFPWRGOODV IH,min1 msecRESET#REQ[4:0]#I/OD0026-00The REQ[4:0]# (Request Command) signals must connect the appropriate pins ofall processor system bus agents. They are asserted by the current bus owner overtwo clock cycles to define the currently active transaction type.Datasheet 97
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Intel ® Pentium ® III Processor f
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Contents1.0 Introduction...........
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Figures1 Second Level (L2) Cache Im
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18 System Bus AC Specifications (TA
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Introduction1.1.2 Processor Naming
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Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

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