201305.pdf 43279KB May 08 2013 11:07:04 PM

More documents

Recommendations

Info

BLUE CONTOUR SHOWS NECKING DUE TOOPPOSITE LINE ENDS FROM LEFT AND RIGHTA KNOWN LITHO HOTSPOTCAN BE IDENTIFIED IN LAYOUTVIA RULES CLASSIFIED AS AYIELD DETRACTOR PATTERNaffecting margins, silicon utilization,silicon failure, and timing closure.Consequently, advanced-nodedesigners must optimize chip manufacturabilityalong with area, speed, andpower. This trend will increase exponentiallyas technology advances to 14 nm.RED MARKER INDICATES A HOTSPOTMANY YIELD DETRACTORPATTERNS CAN BE PUT0282-APEC2014 Ad 7.25x5.125 call for paper.QXD 4/10/13 TOGETHER TO 6:17 CREATE PM Page 1A PATTERN LIBRARYFigure 3 Software helps quantify problems due to LDE and to locally optimize thedevices deviating from the specifications.IdentIfy crItIcal desIgnfeatures usIng dIagnosIsdrIvenyIeld analysIsGeir Eide, Product MarketingManager, Silicon Test SolutionsGroup, Mentor GraphicsDuring the transition to the 28-nmnode, several leading semiconductorcompanies struggled with supply: Theycouldn’t ship enough of their products.Part of the problem was lower-thanexpectedyield. This situation illustrateshow traditional yield learning methodsare running out of steam, largelybecause of the dramatic increase in thenumber and complexity of design-sensitivedefects and longer failure analysiscycle times. These factors have forcedfabless semiconductor companies toarm themselves with new technologies2014March 16–20, 2014Fort Worth Convention CenterFort Worth, TXTHE PREMIER GLOBAL EVENTIN POWER ELECTRONICS TM TMVisit the APEC 2014 web sitefor the latest information!CALL FOR PAPERS!deadline for submission, July 8, 2013, go to web for details:www.apec-conf.orgSPONSORED BY32 EDN | MAY 2013 [ www.edn.com]
such as diagnosis-driven yield analysis(DDYA), which can rapidly identify theroot cause of yield loss and effectivelyseparate design- and process-orientedyield loss.Software-based diagnosis of testfailures is an established method forlocalizing defects during failure analysisfor digital semiconductor devices.Diagnosis software determines thedefect type and location for each failingdevice based on the design description,scan test patterns, and tester faildata. Using statistical analysis, diagnosisresults from a number of failing devicescan be used to effectively determine theunderlying root causes.The primary challenge for yield analysisis dealing with the ambiguity in theresults. For example, more than one locationcould explain the defective behavior,and each suspect location often hasmultiple possible root causes associatedwith it. To better derive the underlyingroot causes represented in a populationof failing devices from test data alone,you need to apply machine learning anddesign statistics, such as tested criticalarea for each layer and total number ofgates tested of any given type 1 .Another way to expand the scopeof DDYA is to include data from DFManalysis (Figure 4). One key motivationbehind this approach is to be ableto prove that a defect found in failureanalysis is a systematic critical feature,and then to learn what about that featurerelates to the defect’s rate of occurrence.Without a DDYA methodologythat can automatically incorporateDFM information, you would need ateam of experts and a lot of experimentationto accomplish this. However, byfirst identifying all locations in a designwith a suspected feature through DFManalysis, any diagnosis results (that is,actual silicon defects) that overlap theselocations can easily be identified andanalyzed to determine whether this correlationalso presents causation. A secondmotivation behind this approach isto determine whether a potential designfix could cure the problem. By identifyingdesign locations that contain theplanned fix, a similar correlation can beperformed before actually implementingthe fix, and the failure rates can becombined 2 .Diagnosis-driven yield analysisappears particularly promising for the 20-and 16-nm nodes in spite of the inherentlimitations of immersion lithography.SPICE SImulatIonChallEngES for DfYaPPlICatIonSDr Bruce W McGaughy,Chief Technology Officer andSenior Vice President of Engineering,ProPlus Design SolutionsProcess variations, especially localrandom variations, are making DFY a10:05 AMYour first board isready to test.9:00 AMYour circuit design isdone and you’re readyto make a prototype.11:48 AMWhy not try a differentapproach before youhead to lunch?ProtoMat ® Benchtop PCB Prototyping MachineWhat would your day look like tomorrow if you couldcut yourself free from the board house and producetrue, industrial quality PCBs right at your desk?LPKF’s ProtoMat benchtop prototyping systems arehelping thousands of engineers around the worldtake their development time from days and weeksto minutes and hours. In today’s race to market,it’s like having a time machine.www.lpkfusa.com/pcb1-800-345-LPKFmust-have methodology for sub-65-nmdesign. A DFY methodology comprisesthree critical components: statisticaltransistor model extraction, yield predictionand analysis, and a powerfulstatistical simulation engine. An integratedsolution with all three componentsprovides added efficiency andconsistency.The heart and soul of DFY is thesimulation engine. Until recently, mostsimulators have not been well suited as1:03 PMYour second board isready to test.5:00 PMNice work. You justshaved weeks off yourdevelopment schedule.3:14 PMAfter a few tweaks,you’re ready to makeyour finished board.4:09 PMYour finished board isready to go.“You can’t beat an LPKF systemfor prototyping. We do up tothree iterations of a designwithin a day.”Leonard WeberAgilent[ www.edn.com]
Page 1 and 2: Primary LogoMAY 2013www.edn.comIssu
Page 3: MAY 2013www.edn.comIssue 5Teardown:
Page 6 and 7: The Trusted Leaderfor Any Measureme
Page 8 and 9: www.mouser.comThe Newest Products f
Page 11 and 12: onlineJOIN THE CONVERSATIONComments
Page 13 and 14: aND DirEctorPatrick Mannion1-631-54
Page 15 and 16: Baseband & RFMIMO & FadingRohde & S
Page 17 and 18: Your work is fast-paced.Now there
Page 19 and 20: Analog Devices, MathWorks offerengi
Page 21 and 22: pulseTI introduces first eight-chan
Page 23 and 24: LEDrivIRHigh-Voltage Buck Control I
Page 25 and 26: Three banks of plastichousings cont
Page 27 and 28: CST STUDIO SUITE 2013Make the Conne
Page 29 and 30: DESIGN FORMANUFACTURING&YIELDWITHOU
Page 31 and 32: the DFM issues that provide the hig
Page 33: 10 MHz Distribution Amplifiers• S
Page 37 and 38: FastSPICE simulators employ aggress
Page 39 and 40: CELEBRATINGTHEARTOFENGINEERINGEDN A
Page 41 and 42: help people witha damaged skeleton,
Page 43 and 44: Value Instruments:The quality you e
Page 45 and 46: ANALOG ICs: AD9670/71OCTAL ULTRASOU
Page 47 and 48: which often burden other aspects of
Page 49: SPECIAL SECTIONTOP 25GLOBALDISTRIBU
Page 52 and 53: We Do Business Your WayCatalogOnlin
Page 54 and 55: Special SectionUlysses and theSiren
Page 56 and 57: Special SectionNew dynamicsAt the s
Page 58 and 59: Special SectionDid lessons from the
Page 60 and 61: Special Sectionseeing how useful th
Page 62 and 63: Special Sectionvs.Resolving designc
Page 64 and 65: Special SectionAmerica’sdeclared(
Page 66 and 67: Special SectionTips for designengin
Page 68 and 69: Special SectionTOP 25 Global Electr
Page 70 and 71: Special SectionDuelingswordsin theE
Page 72 and 73: Special SectionThe anti-counterfeit
Page 74 and 75: special sectioninventory and decidi
Page 77 and 78: designideasreaderS SOLVe deSIGN PrO
Page 79 and 80: ANALOGINTEGRATIONISN’T FOREVERYON
Page 81 and 82: INNOVATORS THINK STATUS-QUOIS LATIN
Page 83 and 84: Congratulationsto the 2013 ACE Awar
Page 85 and 86:
advertisementA Robust 10MHz Referen
Page 87 and 88:
designideasCLASSICSOriginally publi
Page 89 and 90:
Top GunS.Ip&E SoLuTIonS FRoM AVnETY
Page 91 and 92:
productroundupSenSorS/TranSducerSPr
Page 93 and 94:
minated with either a cable in a co
Page 95 and 96:
No other oscilloscope can touch it.
Page 97 and 98:
No other oscilloscope can touch it.
show all

201305.pdf 43279KB May 08 2013 11:07:04 PM

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?