201305.pdf 43279KB May 08 2013 11:07:04 PM

such as diagnosis-driven yield analysis(DDYA), which can rapidly identify theroot cause of yield loss and effectivelyseparate design- and process-orientedyield loss.Software-based diagnosis of testfailures is an established method forlocalizing defects during failure analysisfor digital semiconductor devices.Diagnosis software determines thedefect type and location for each failingdevice based on the design description,scan test patterns, and tester faildata. Using statistical analysis, diagnosisresults from a number of failing devicescan be used to effectively determine theunderlying root causes.The primary challenge for yield analysisis dealing with the ambiguity in theresults. For example, more than one locationcould explain the defective behavior,and each suspect location often hasmultiple possible root causes associatedwith it. To better derive the underlyingroot causes represented in a populationof failing devices from test data alone,you need to apply machine learning anddesign statistics, such as tested criticalarea for each layer and total number ofgates tested of any given type 1 .Another way to expand the scopeof DDYA is to include data from DFManalysis (Figure 4). One key motivationbehind this approach is to be ableto prove that a defect found in failureanalysis is a systematic critical feature,and then to learn what about that featurerelates to the defect’s rate of occurrence.Without a DDYA methodologythat can automatically incorporateDFM information, you would need ateam of experts and a lot of experimentationto accomplish this. However, byfirst identifying all locations in a designwith a suspected feature through DFManalysis, any diagnosis results (that is,actual silicon defects) that overlap theselocations can easily be identified andanalyzed to determine whether this correlationalso presents causation. A secondmotivation behind this approach isto determine whether a potential designfix could cure the problem. By identifyingdesign locations that contain theplanned fix, a similar correlation can beperformed before actually implementingthe fix, and the failure rates can becombined 2 .Diagnosis-driven yield analysisappears particularly promising for the 20-and 16-nm nodes in spite of the inherentlimitations of immersion lithography.SPICE SImulatIonChallEngES for DfYaPPlICatIonSDr Bruce W McGaughy,Chief Technology Officer andSenior Vice President of Engineering,ProPlus Design SolutionsProcess variations, especially localrandom variations, are making DFY a10:05 AMYour first board isready to test.9:00 AMYour circuit design isdone and you’re readyto make a prototype.11:48 AMWhy not try a differentapproach before youhead to lunch?ProtoMat ® Benchtop PCB Prototyping MachineWhat would your day look like tomorrow if you couldcut yourself free from the board house and producetrue, industrial quality PCBs right at your desk?LPKF’s ProtoMat benchtop prototyping systems arehelping thousands of engineers around the worldtake their development time from days and weeksto minutes and hours. In today’s race to market,it’s like having a time machine.www.lpkfusa.com/pcb1-800-345-LPKFmust-have methodology for sub-65-nmdesign. A DFY methodology comprisesthree critical components: statisticaltransistor model extraction, yield predictionand analysis, and a powerfulstatistical simulation engine. An integratedsolution with all three componentsprovides added efficiency andconsistency.The heart and soul of DFY is thesimulation engine. Until recently, mostsimulators have not been well suited as1:03 PMYour second board isready to test.5:00 PMNice work. You justshaved weeks off yourdevelopment schedule.3:14 PMAfter a few tweaks,you’re ready to makeyour finished board.4:09 PMYour finished board isready to go.“You can’t beat an LPKF systemfor prototyping. We do up tothree iterations of a designwithin a day.”Leonard WeberAgilent[ www.edn.com]