201305.pdf 43279KB May 08 2013 11:07:04 PM

FastSPICE simulators employ aggressivepartitioning, event-driven multirateschemes, transistor table models,hierarchical array reduction, and thelike. All of these techniques are “tuned”for typical circuit types and operatingconditions and, in most cases, requirefurther “tuning” with special optionsby the designer.With yield prediction, designerstrack circuit behavior at the marginsof the design and process space wherebuilt-in tuning may not apply, leadingto accuracy problems. Furthermore,the designer cannot manually tune theoptions for marginal operating conditionsduring statistical simulation.Finally, techniques such as table modelsand hierarchical array reduction willnot work when every transistor in thecircuit has a different variation.The ideal solution would be toextend the capabilities of SPICE tocover the performance and capacityprovided with FastSPICE. ParallelSPICE simulators have taken over someof the space covered by FastSPICEwith 10× or more speedup over traditionalSPICE.Advancement for giga-scale simulatorsis coming from highly optimizeddata structures and core algorithmsbuilt for high-performanceparallelization and capacity. GigascaleSPICE is the principle behindProPlus’s NanoSpice, the simulationengine of its DFY solution builtaround NanoYield, yield predictionand improvement, and BSIMProPlus,statistical model extraction.EDNreferences1 Benware, B, et al, “Determining aFailure Root Cause Distribution From aPopulation of Layout-Aware ScanDiagnosis Results,” IEEE D&T of Computers,Volume 29, Issue 1.2 Schuermyer, C, et al, “IdentifyingSystematic Critical Features Using SiliconDiagnosis Data,” ASMC 2012,http://bit.ly/ZmV2PD.You can reachContributingTechnical EditorBrian Bailey atbrian_bailey@acm.org.[ www.edn.com]