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DAC reference voltage used in developing the analogoutput voltage. The DAC contains a register usedto hold the digital value being converted. This outputregister is loaded by a data transfer from corestorage. As the register is loaded, the DAC convertsthe digital value and provides the correspondinganalog output voltage. The output remains until theregister is changed by another data transfer. Duringdata transfer from core storage, the output registeris force loaded to minimize DAC switchingtransients. Force load means that the register goesdirectly from the previous value to the new valuewithout being reset to 0 in between.Four DAC mods (1, 2, 3, and 4) are available toprovide two basic types of analog voltage output.DAC Mod 1 and Mod 2DAC 's mod 1 and mod 2 provide unipolar analogvoltage output from ten-bit digital input. This analogvoltage output is suitable for operating analogcontrollers, strip chart recorders, and other displays.The mod 1 provides one analog output point.Therefore, a maximum system configuration populatedwith mod 1 DAC 's provides 64 analog outputpoints. The mod 2 has two separate digital-toanalogconverters in one housing and two analog outputpoints. A maximum system configuration populatedwith mod 2 DAC 's provides 128 analog outputpoints.The format of the ten-bit digital data sent fromcore storage for conversion is:S Digital Value13 1513- Bit Resolution Format 117879 IIt is frequently a requirement in hybrid computingand often an advantage in other applications tofurnish output at several analog output points simultaneously.By using an optional buffer register foreach of these analog output points, the buffers canbe preloaded as data is received from the P-C.After the buffers are loaded, an execute I/O (XIO)control with modifier bit 9 on is executed, causingall DAC registers to be simultaneously loaded directlyfrom their buffer registers.Precision Voltage ReferenceThe precision voltage reference (PVR) feature is requiredto supply the DAC reference voltage. Eachfeature can supply up to eight analog output pointsand is available in two models.The mod 1 precision voltage reference is usedwith mod 1 or mod 2 DAC 's to provide ten-bitresolution unipolar analog output. The mod 2 precisionvoltage reference is normally used with mod 3or mod 4 DAC 's to provide 13-bit resolution bipolaranalog output. The mod 2 precision voltage referencemay be used with mod 1 or mod 2 DAC 's when it isdesired to mix the two kinds of output in a single1856 Analog Output Terminal. However, it is moreeconomical to use the mod 1 for each full group ofeight ten-bit resolution unipolar output points.Analog Output Driver AmplifierDigital ValueDAC Mod 3 and Mod 410 1510- Bit Resolution Format1 17878 1DAC 's mod 3 and mod 4 provide bipolar analog voltageoutput suitable for hybrid systems. This outputis obtained from digital input consisting of 13 bitsplus sign. Negative digital input values are handledin 2's complement form.Mod 3 provides one analog output point. Therefore,a maximum system configuration populatedwith mod 2 DAC 's provides 64 analog output points.Mod 4 has two separate digital-to-analog convertersin one housing and two analog output points. A maximumsystem configuration populated with mod 4DAC 's provides 128 analog output points.The format of the 13-bit (plus sign) digital datasent from core storage for conversion is:The analog output driver amplifier is an optionalfeature that can be installed on each analog outputpoint. This amplifier provides a ±10 volt analogoutput signal and permits operation of an analogoutput point with a wide range of load impedances.The output impedance of the DAC 's is 10,000 ohms.To match loads differing greatly from this value, ananalog output driver amplifier with an output impedanceof less than 0.6 ohm may be used. The analogoutput driver amplifier may also be used to increasethe DAC output from its normal 5 volts to 10 volts.DIGITAL AND ANALOG OUTPUT ADDRESSINGDigital and analog output points share a group of addresses.The decimal range of addresses is 0through 127.As shown in Figure 50, each digital output controlordered is assigned 16 addresses beginning withaddress 127 for the first group of 16 points. Address126
DigitalOutputControl65Digital OutputDigitalOutputAdapterAddresses00 - 15not availablefordigital output282726252423222120191817Decimal -Addre s (Modifiers)Group No.(16 pointseach )320320320320320320320320320320320321010001020304Os06070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263DAC Mod2 or 4Output1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2ndlst2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2ndlst2nd1st2ndAnalog Output1 or 3Output1st1st1st1st1st1st1st1st1st1stlst1st1st1st1st1stlst1st1st1st1st1st1st1st1st1st1st1st1stDAC No.within1856* Not available when the first digital output control is in 1826.**Not available when the first digital output control is in 1801.1st1st1st1234123412341234123412341856DigitalOutputControlDigital OutputDigitalOutputAdapter16Decimal - Addre s (Modifiers)Group No,(16 pointseach )321st 0(Model 1)31524140322nd 0(Model 2)3132120323rd 0(Model 1)31123100324th 0(Model 2)39280325th 0(Model 1)372260326th 0(Model 2)3521 **234123440327th 0(Model 1)3**.23120328th 0(Model 2) 3201646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127DAC Mod2 or 4Output1st2nd1st2nd1st2nd1st2nd1st2nd1st2ndlst2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2nd1st2ndlst2nd1st2ndAnalog Output1 or 3Output1st1stlst1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1st1stlst1st1st1st1st1st1stDAC No.within18562342341234123423412341234123418569th(Model 1)10th(Model 2)11th(Model 1)12th(Model 2)13th(Model 1)14th(Model 2)15th(Model 1)16th(Model 2)2,I6711 1Figure 50. Digital and Analog Output AddressesDigital and Analog Output 127
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File No. 1800-01Order No. GA26-5918
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ContentsINTRODUCTION 1SYSTEM DESCRI
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Thermocouple Conversion ExampleConv
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Status Character 2412790 ADAPTER PR
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Processor - ControllerCoreStorageOu
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Page of GA26-5918-8Revised July 14,
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egister or the index register speci
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Short InstructionDDOne WordInstruct
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Instruction SetThe 1800 system inst
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LOAD ACCUMULATOR (LD)FORMATS oitamw
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STORE ACCUMULATOR (STO)FORMATSF 0 O
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LOAD INDEX (LDX)0 OP F T Disp 151 0
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STORE STATUS (STS) Store Status Fun
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LOAD STATUS (LDS)117165 A1DESCRIPTI
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SUBTRACT DOUBLE (SD).fartzaielTmEas
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DIVIDE (D)FORMATS0 OP F T DispF T I
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LOGICAL EXCLUSIVE OR (EOR)'FORMATS
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SHIFT LEFT A AND Q (SLT)altkae..,.:
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SHIFT RIGHT LOGICAL A (SRA)FORMAT s
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ROTATE RIGHT A AND Q (RTE)FORMAT ta
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BRANCH OR SKIP ON CONDITION (BSC OR
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a4.-4KA4rE4.7.9.4.&.4VA/M4:14/24...
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',V.71..1.41VV4-02,P2A,V4,1%1,L—N
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COMPARE (CMP)FORMATS0 OP F T Disp 1
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MachineCyclesAUGEND (A-reg) and ADD
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chain is accomplished as follows: T
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InterruptTo allow for coordination
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After a request for service has bee
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2. The forced BSI with indirect add
Page 84 and 85: Storage ProtectionStorage protectio
Page 86 and 87: Page of GA26-5918-8Revised January
Page 88 and 89: Processor-Controller ConsoleThe pro
Page 90 and 91: 117674,Figure 23. Console Pushbutto
Page 92 and 93: Page of GA26-5918-8Revised July 14,
Page 96 and 97: DATA FLOW DISPLAYSSix rows of light
Page 98 and 99: This command causes the console int
Page 100 and 101: High -LevelHigh -Level Low-LevelLow
Page 104 and 105: CUSTOM ELEMENT: This element is ava
Page 106 and 107: The clock stop period does not dire
Page 108 and 109: Numberingwithin 18511851's withMult
Page 110 and 111: selected analog signal to a digital
Page 114 and 115: 0 1 2 3 4 5 8 7 0 9 10 14 15Indicat
Page 116 and 117: Direct Program Control Operations P
Page 118 and 119: Temp TempF C1652° 9001472° 81292
Page 120 and 121: 2. Determine the ADC reading (Q val
Page 122 and 123: Digital InputDigital input features
Page 124 and 125: ead operation without external sync
Page 126 and 127: AdapterFirstSecondThirdFourthFifthS
Page 128 and 129: the next input group address (conta
Page 130 and 131: status word (PISW), the PISW is rea
Page 132 and 133: ProcessorControllerOut Bus(16 - Bit
Page 136 and 137: 126 is assigned to the second group
Page 138 and 139: The input/output control command (I
Page 142 and 143: 1053/1816 Printer IOCC'sCE ModeSpec
Page 144 and 145: Keyboard entries are not printed au
Page 146 and 147: error is detected, the program may
Page 148 and 149: the keyboard into a storage-protect
Page 150 and 151: Channel••• ••••• 14
Page 152 and 153: READER ANY ERROR: This indicator tu
Page 156 and 157: Even-Numbered ColumnsOdd-Numbered C
Page 158 and 159: 1442 DSW Interrupt IndicatorsFigure
Page 160 and 161: The preceding examples show that if
Page 162 and 163: CharHexCore Storage BitsTypebar2 5
Page 166 and 167: CE PRINTER BUSY: When the 1443 is i
Page 168 and 169: DrumDownDRUM FAST RUN: This switch
Page 170 and 171: 1627 DSW Noninterrupt IndicatorsFig
Page 172 and 173: 120255A1Each track is divided into
Page 174 and 175: This command places the disk storag
Page 176 and 177: ANY ERROR: This indicator turns on
Page 178 and 179: LogicalDataRecordIBGapLRCIBGap.._01
Page 180 and 181: A tape mark read from seven-track t
Page 182 and 183: Modifier bits perform the five func
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an XIO initialize read operation wi
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Communications AdapterINTRODUCTIONT
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character (bit positions 0 through
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Bit PositionsP, 7, 6, 54, 3, 2, 100
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Standard replies as well as NAK cau
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either seeking characters received
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CA IOCC'sInitialize Write0 15 0 4 8
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TIMEOUT: This indicator turns on, c
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0 I 2 3 4 5 6 7 8 9 10 11 i2 13 14
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ETB, ETX, AND ENQ: These characters
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.■••.0■-3toCOc.nroz0F21.0fa
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Selector ChannelThe selector channe
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CCW Word 1 CCW Word 2 CCW Word 315B
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limited to the number of sense byte
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CSW Word 1 CSW Word 2 CSW Word 3 CS
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CSW Word 2 CSW Word 3CSW Word 40 3
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Termination of an operation with a
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Device end, when subsequently provi
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System /360 AdapterINTRODUCTIONThe
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specified by the channel command wo
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ATTENTION: This status indicates th
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HALT: This bit turns on, causing an
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Start Byte AS Address Byte Device A
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Read data request causes the adapte
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If a 1053 Printer is addressed by t
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specific 16-word block within the c
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LCCBWord1Address Word(Active Frame)
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channel active is interrogated. If
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Form GA26-5918-8Page Revised 10/1/7
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AREA STATION LOCAL I/O TRANSACTION
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244Form GA26-5918-8Page Added 10/1/
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When all segments are bypassed modi
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0. It can occur only during a read
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HexadecimalValueDouble Compare (DCM
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Appendix B. I/O Device AddressingTh
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1054 AND 1055 PAPER TAPEWRITE: Punc
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INITIALIZE WRITE: Move contents of
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INITIALIZE READ: Move tape data to
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AREA FEATURE 0 1 2 3 4 5 6 7 8 9•
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Clear (Continued)Storage (Continued
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Converting Thermocouple Characteris
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4Input/Output Control (Continued)On
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Loop Channel (Continued)Control Blo
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Pulse OutputDescription of 125Timer
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Storage ProtectBit (S) 10Bit Light
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1053 Printer (Continued)Maximum Rat
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1810 Disk Storage (Continued)Read/W
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IBM Technical Newsletter File Numbe
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^;``
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• READER'S COMMENT FORM•▪ IBM
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• READER'S COMMENT FORM• IBM 18
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• READER'S COMMENT FORM• IBM 18
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