Systems Reference Library - All about the IBM 1130 Computing ...

0 I 2 3 4 5 6 7 8 9 10 11 i2 13 14 15I II 1 LI111111L1514131211109Indicator NameB7 Transmit Line Bit Trigger6 End Trigger5 Text Trigger4 Transparent Trigger3 Not Clear to Send2 Character Trigger 11 Character Phase0 CE Diagnostic *Active only when wired by CE. Otherwise always 1Figure 101. CA Diagnostic Device Status WordSERDES Bits (0-7)II1745131initialization to the time a SYN SYN sequence isdetected, indicating character phase.CHARACTER TRIGGER 1: This indicator reflectsthe status of the first bit in the character counter.This counter is held reset except when the adapteris transmitting or receiving the following:1. The initial pre-SYN and SYN SYN sequence.2. SYN characters in the data stream.3. Characters following an end character.Under these conditions, the indicator alternatelyturns on and off at each character time.NOT CLEAR TO SEND: This indicator is on whenthe data set is not in transmitting state.TRANSPARENT TRIGGER: This indicator is turnedon by a DLE STX sequence. It is turned off by aDLE followed by an ETB, ITB, ETX, or ENQ.A clear CA function also resets this trigger.TEXT TRIGGER: This indicator is turned on bythe first character after SOH or STX in a message.It is reset when the mode is changed from transmitto receive mode or vice versa.A clear CA function also resets this trigger.END TRIGGER: This indicator turns on if any one ofthe following characters is recognized: ETB, ETX,ITB, or ENQ. It also turns on if NAK, EOT, orDLE turnaround is recognized and not preceded byan SOH or SIX in the data stream.In transparent mode, only ETB, ETX, ITB, andENQ are recognized, and each must be preceded by asingle DLE.This indicator is reset at end-character-decodetime or by a clear CA function.TRANSMIT LINE BIT TRIGGER: This indicatorreflects the status of the transmit line bit trigger andis on whenever a 1-bit (mark) is being transmitted onthe line.SERDES: These eight indicators reflect the status ofSERDES bit positions 0 through 7. The contents ofSERDES are shifted from bit position 0 to bit position7. Therefore, SERDES output to the line is via bitposition 7, and SERDES input from the line is via bitposition O.In two-wire systems, transmitted data returnsto the SERDES input after a certain delay; normallythe delay equals the transmit time through the dataset. However, if the switch on the data set cable isset to TEST, the delay equals one bit time.DATA SET CONTROL LINE OPTIONSVarious options are provided for controlling the dataterminal ready and request-to-send control lines tothe data set. These options allow the customer todesign a method of data set control that is suitable forthe types of data sets and transmission lines used aswell as for the particular application.The method used to control data set ready andrequest-to-send are selected and assigned, duringsystem installation, according to the options selectedby the customer.Data Terminal ReadyThree methods for controlling the data terminalready line are available. These methods are describedin the following paragraphs.The first method of control is.to provide a continuousdata terminal ready signal to the data set. In thiscase, data terminal ready is on continuously and is notcontrolled by the program or conditions occuring duringoperation. This method of control may be used in(1) four-wire operations, (2) two-wire leased lineoperations, or (3) two-wire switched line operationsthat do not use the ringing interrupt feature.The second method of control is to provide a dataterminal ready signal to the data set when the lineadapter is first initialized by the program for a192