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STORE STATUS (STS) Write or Clear Storage Protect Bit FunctionFORMAT0 OP F T 'A DO Coed 15 0 Address 15, I ijo,o,o,o,o, „ „ I „ , , I I2 C-F 4 or C 0 or 1 X X X X117164 B1DESCRIPTIONThe storage protect bit in the core-storage location specifiedby the effective address (EA) of the instruction iswritten or cleared as indicated by bit position 15 of theinstruction being 1 or 0, respectively.A long format instruction (F bit is 1) must be usedand bit 9 (BO) of the instruction must be 1 for a writeor clear storage protect bit function; otherwise a storestatus function is performed as described on the precedingpage.The preceding description of the write or clear storageprotect bit function is performed only if the write storageprotect bits switch on the P-C console is positioned onYES. As long as this switch is on YES, the program hasthe ability to write or clear storage protect bits as describedin the preceding paragraphs. If the switch is onNO, this instruction performs as a no-op (no-operation).THE CARRY AND OVERFLOW INDICATORS are notchanged by this instruction.EXAMPLES714 .12Label21 25Assembler Language CodingOperation27 30FT323335 40SeeNoteHexadecimalValueEquivalent Machine Language InstructionDescription, 1 S Il l s I L A,D,D,R, ,1/14,012C40XXXX Clear storage protect bit in CSL at EA (Addr)I , I MIS, L AA) il) p , , 1/ 1411 ,2C41XXXX Write storage protect bit in CSL at EA (Addr)I 1 I S I T I S, L I A,D,D,R,, ,/ 1 4,0 12D40XXXX Clear storage protect bit in CSL at EA (Addr+XR I)1 i I S IT 'S ., L I A,D,D,R, III 4,1 ,2D4IXXXX Write storage protect bit in CSL at EA (Addr+XR I), , 1 S I T I S, L 2 A,D,D,R 1 , ,/ .4 1 0 1 2E4 OXXXX Clear storage protect bit in CSL at EA (Addr+XR2)1 1 1 S,T,S, L 2 A,D,D,R 1 , 1 / 1 4,1 , 2E41XXXX Write storage protect bit in CSL at EA (Addr+XR2)I I I I S,T,S, L 3 A,D,D,R, , ,/ 1 4 10, 2F40XXXX Clear storage protect bit in CSL at EA (Addr+XR3), , S,T,S, L 3 A,D,D1R1, 1/,41 II 2F41XXXX Write storage protect bit in CSL at EA (Addr+XR3)I 1 S,T,Si I A,D,D,R 1 , ,/,4,0, 2CCOX.XXX Clear storage protect bit in CSL at EA (V in CSL at Addr), , 1 S iT I S, I A,D,D,R, I 1,4 1 I 1 2CCIXXXX Write storage protect bit in CSL at EA (V in CSL at Addr)I i I I I i 1 1 1 1 1 1 1 1I I I S,T,S, I I A,D,D,R, ,1/14,0, 2DCOXXXX Clear storage protect bit in CSL at EA (V in CSL atI 1 1 1 1 I t 1 1 1 1 1 1 1 1"Addr+XR 1")1 i I S,T,S, I I A,D,D,R; ,,/,41112DC1XXXX Write storage protect bit in CSL at EA (V in CSL atI I I I I I 1 1 1 1 I I 11 "Addr+XR I")1 I I S,T,S, I 2 A, D I DR! , ,/,4 10, 2ECOXXXX Clear storage protect bit in CSL at EA (V in CSL atI I I I i I I 1 I 1 1 1 I I I "Addr+XR2")I 1 S,T,S, I 2 A,D,D,R,,,/ ,4, I, 2ECIXXXX Write storage protect bit in CSL at EA (V in CSL atI i i 1 1 1 1 i I I 1 1 1 "Addr+XR2")I 1 I S,T,S, I 3 A,D,D,R, ,,/,4,0, 2FCOXXXX Clear storage protect bit in CSL at EA (V in CSL atI I I I I I i I ii i I t I "Addr+XR3")i 1 SiTIS, 1 3 4,0 1 1),R, , J 1 4,1 1 2FCIXXXX Write storage protect bit in CSL at EA (V in CSL at1 I 1 I 1 I 1 i I "Addr+XR3")A With MPX Version 3, the storage protect operand (/40 and /41) can besymbolically represented by U and P, respectively.FormatLongInstructionDirectAddressingLongInstructionIndirectAddressingInstruction Set 23STS