Intel 80200 Processor based on Intel XScale Microarchitecture

Summary Table of ChangesSpecification ChangesNo.SteppingsA-0 A-1 B-0 C-0 D-0Page Status Specification Changes1 X X X X X 39 Doc Revised and moved to Specification Clarification 2.2 X X X X X 36 Doc Drowsy Mode has been De-Specified3 X X 36 New ECC Disable Bit Available on the C-0 and D-0 Step4 X 36 200MHz <strong>Processor</strong> Available5 X 37 Extended Temperature Products AvailableSpecification ClarificationsNo.SteppingsA-0 A-1 B-0 C-0 D-0Page Status Specification Clarifications1 X X X X X 39 Doc TRST# Usage2 X X X X X 39 Doc STRD and LDRD Instructions3 X X X X X 39 Doc Write Coalescing with the <strong>Intel</strong> ® 80312 I/O Companion ChipDocumentation ChangesNo. Document Revision Page Status Documentation Changes1 273411-002 40 Doc Section C.2.4.1, Table C-42 273411-002 40 Doc Example 6-3 on page 6-12 may not work properly3 273411-002 41 DocFigure 13-12 on page 13-39 and Figure 13-13 on page 13-41 show incorrectsignal states4 273411-002 41 Doc Section A.2 on page A-2 has incorrect text5 273411-002 41 Doc Section B.2.3.1 on page B-6 has incorrect text6 273411-002 41 Doc Table 7-3 on page 7-4 shows incorrect register access7 273411-002 41 Doc Table 7-15 on page 7-13 shows incorrect register access8 273411-002 42 DocAll References to Drowsy Mode should be Removed from the <strong>80200</strong>Developer’s Manual9 273411-002 42 Doc Table 11-6 on page 11-10 has a new bit function for ECTST.3110 273411-002 42 Doc Figure C-2 on page C-7 shows an incorrect state11 273411-002 42 Doc Example code is incorrect on page 13-1512 273411-002 42 Doc Example code is incorrect on page 13-4513 273411-002 42 Doc Number of clocks is incorrect on page 8-214 273411-002 43 Doc Figure 10-12 on page 10-22 shows incorrect BE# value15 273411-002 43 Doc Example code is incorrect on page 7-1710 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update