Intel 80200 Processor based on Intel XScale Microarchitecture

Summary Table of ChangesErrata (Sheet 2 of 2)No.SteppingsA-0 A-1 B-0 C-0 D-0Page Status Errata29 X X X X X 22 NoFix Load immediately following a DMM flush entry is also flushed30 X X X X X 22 NoFix Trace Buffer does not operate below 1.3 V31 X X 23 FixedThumb branch with the Branch Target Buffer enabled, can goto the wrong address32 X X X X X 23 NoFix Back to back external aborts can cause a hang33 X X X X X 23 NoFix Data Cache Unit can stall for a single cycle34 X X X X X 24 NoFixAborted Store that Hits the Data Cache May MarkWrite-Back Data as Dirty35 X X X 24 FixedData Cache Unit Signals Incorrect Number of Misses orMemory Operations to the Performance Monitoring Unit36 X X X 25 Fixed Incorrect ECC Attribute Used on Instruction Fetch37 X X X 25 Fixed Performance Monitoring Unit May Miscount SWI/UNDEFs38 X X X 26 Fixed39 X X X 27 Fixed40 X X X X 28 Fixed41 X X 31 Fixed42 X X 31 Fixed43 X X X X X 32 NoFix44 X X X X X 32 NoFix45 X X X X 33 Fixed46 X X 34 Fixed47 X X X X X 34 NoFix48 X X X X X 35 NoFix49 X X X X X 35 NoFixTLB Lookup in Special Debug State May Use Incorrect PageAttribute Bit Values on Subsequent Code FetchesCP15 Data Cache Unlock Command Can Cause Unlock inUser Mode or when Flushed from the Pipe in SupervisorModeStore to cacheable memory, interrupted by an exception,may inadvertently write to memoryData cache dirty bits may be corrupted if a line invalidate isfollowed immediately by a storeData cache dirty bits may be corrupted if a bus error on acache line fill is followed immediately by a storePerformance Monitor Unit event 0x1 can be incrementederroneously by unrelated eventsIn Special Debug State, back-to-back memory operations —where the first instruction aborts — may cause a hangInstruction Memory Management Unit address translation isturned off for the first fetch after exiting Special Debug StateData cache dirty bits may be corrupted if a store to cacheablememory occurs during a tag replacement for a differentcache lineAccesses to the CP15 ID register with opcode2 > 0b001returns unpredictable valuesDisabling and re-enabling the MMU can hang the core orcause it to execute the wrong codeUpdating the JTAG parallel registers requires an extra TCKrising edge<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 9