Intel 80200 Processor based on Intel XScale Microarchitecture

Errata36. Incorrect ECC Attribute Used on Instruction FetchProblem:Workaround:On rare occasions an instruction fetch uses the wrong ECC attribute. This only occurs when ainstruction fetch return from the external bus lines up with a invalidate of the BTB. BTBinvalidates are caused by PID changes, or MCR commands which invalidate the instruction cacheor BTB. When this occurs a new fetch may get the ECC attribute of the returning fetch instead ofthe requested line. This can cause one of two things to happen:1. A fetch, that should be checked for ECC errors, is not checked.2. A fetch, that should not be checked for ECC errors, generates an ECC prefetch abort in anon-ECC memory region. When this happens, the prefetch abort handler can usually safelyreturn to the aborting instruction. When however, the processor was already in abort mode asthis occurred, r14 is modified, and the link to the original process may be lost.This errata is rare because it requires the processor to be executing from an ECC protected region,a branch to a non-ECC region followed by a BTB invalidate all lined up appropriately with twoseparate instruction cache misses.Software workarounds include:1. Do not use ECC. This errata does not apply when all page table entries are marked asnon-ECC regions.2. Do not flush the BTB or change the PID while in abort mode until the link register and SPSRhas been saved. When an ECC prefetch abort is generated for a non-ECC region, simply retrythe offending instruction.3. Drain the fill buffers before causing a BTB invalidate. Make sure the drain command and theinvalidate have the same memory ECC attributes.Status: Fixed. Fixed on C-step. See the Table “Summary Table of Changes” on page 7.37. Performance Monitoring Unit May Miscount SWI/UNDEFsProblem:Workaround:In some cases, depending on data cache activity, the signal coming from the debug unit indicatingto the Performance Monitoring Unit that a software interrupt or an undefined opcode event hasoccurred may be ignored. This leads to fewer than the actual number of software interrupts orundefined opcodes executed being reported in the PMU count.No workaround.Status: Fixed. Fixed on C-step. See the Table “Summary Table of Changes” on page 7.<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 25