Intel 80200 Processor based on Intel XScale Microarchitecture

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PrefacePrefaceThis document is an update to the specifications contained in the Affected Documents/RelatedDocuments table below. This document is a compilation of device and documentation errata,specification clarifications and changes. It is intended for hardware system manufacturers andsoftware developers of applications, operating systems, or tools.Information types defined in Nomenclature are consolidated into the specification update and areno longer published in other documents.This document may also contain information that was not previously published.Affected Documents/Related DocumentsTitle Order #<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual 273411<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Datasheet 273414<strong>Intel</strong> ® 80310 I/O <strong>Processor</strong> Chipset with <strong>Intel</strong> ® XScale Microarchitecture Design Guide 273354<strong>Intel</strong> ® 80312 I/O Companion Chip Developer’s Manual 273410<strong>Intel</strong> ® 80312 I/O Companion Chip Specification Update 273416NomenclatureErrata are design defects or errors. These may cause the <strong>Intel</strong> ® 80303 I/O <strong>Processor</strong>’s behavior todeviate from published specifications. Hardware and software designed to be used with any givenstepping must assume that all errata documented for that stepping are present on all devices.Specification Changes are modifications to the current published specifications. These changeswill be incorporated in any new release of the specification.Specification Clarifications describe a specification in greater detail or further highlight aspecification’s impact to a complex design situation. These clarifications will be incorporated inany new release of the specification.Documentation Changes include typos, errors, or omissions from the current publishedspecifications. These will be incorporated in any new release of the specification.Note:Errata remain in the specification update throughout the product’s lifecycle, or until a particularstepping is no longer commercially available. Under these circumstances, errata removed from thespecification update are archived and available upon request. Specification changes, specificationclarifications and documentation changes are removed from the specification update when theappropriate changes are made to the appropriate product specification or user documentation(datasheets, manuals, etc.).6 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update
Summary Table of ChangesSummary Table of ChangesThe following table indicates the errata, specification changes, specification clarifications, ordocumentation changes which apply to the <strong>Intel</strong> ® 80303 I/O <strong>Processor</strong> product. <strong>Intel</strong> may fix someof the errata in a future stepping of the component, and account for the other outstanding issuesthrough documentation or specification changes as noted. This table uses the following notations:Codes Used in Summary TableSteppingPageX: Errata exists in the stepping indicated. Specification Change orClarification that applies to this stepping.(No mark)or (Blank box): This erratum is fixed in listed stepping or specification change does notapply to listed stepping.(Page):Page location of item in this document.StatusDoc:PlanFix:Fixed:NoFix:Document change or update will be implemented.This erratum may be fixed in a future stepping of the product.This erratum has been previously fixed.There are no plans to fix this erratum.RowChange bar to left of table row indicates this erratum is either new ormodified from the previous version of the document.<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 7
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Page 3 and 4: ContentsRevision History ..........
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Page 9 and 10: Summary Table of ChangesErrata (She
Page 11 and 12: Identification InformationIdentific
Page 13 and 14: ErrataErrata1. Branch and Link inst
Page 15 and 16: Errata9. Last abort is missed on re
Page 17 and 18: Errata17. Boundary scan is not full
Page 19 and 20: Errata19. Back to back I/O transact
Page 21 and 22: Errata25. Dirty bits are not cleare
Page 23 and 24: Errata31. Thumb branch with the Bra
Page 25 and 26: Errata36. Incorrect ECC Attribute U
Page 27 and 28: Errata39. CP15 Data Cache Unlock Co
Page 29 and 30: ErrataIf there is a flag used to co
Page 31 and 32: Errata41. Data cache dirty bits may
Page 33 and 34: Errata45. Instruction Memory Manage
Page 35 and 36: Errata48. Disabling and re-enabling
Page 37 and 38: Specification Changes5. Extended Te
Page 39 and 40: Specification ClarificationsSpecifi
Page 41 and 42: Documentation ChangesLOOP1:LOCKLINE
Page 43 and 44: Documentation Changes14. Figure 10-

Intel 80200 Processor based on Intel XScale Microarchitecture

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