Intel 80200 Processor based on Intel XScale Microarchitecture

Errata40. Store to cacheable memory, interrupted by an exception, may inadvertentlywrite to memoryProblem:In some cases, if a store to a cacheable region of memory occurs simultaneously with an exception,the store will not be properly cancelled and may update memory. This may occur even if the storedid not have permission to write to that memory region, and no data abort will be recorded at thetime memory is incorrectly modified. It is important that developers review this erratum and assessthe impact to their specific application to ensure that no potential exists for data corruption.This combination of events is required for the erratum to occur:1. A memory operation occurs that requires a cache line fill, which in turn causes a cache lineeviction. For example, a load or prefetch.2. A few cycles later, an exception event occurs. The following exception events will cause theerratum: interrupt, prefetch abort, instruction breakpoint, invalid opcode fault, and imprecisedata abort. A precise data abort may not cause the erratum.3. The instruction which is being flushed by the exception event is a store to write-back memory,and the store address coincides with the cache line that is being evicted to make room for thecache line fill.4. Returning data on the bus causes a data cache stall at a specific cycle.Result:The store writes to memory when it should not. If the store is to write-back memory, the cache lineis evicted and external memory is incorrectly updated as if that store had occurred. The exceptionreturn points to the store instruction.If the store is to write-through memory, the store instruction is properly flushed and externalmemory is not updated.Memory access permissions are not checked before the store updates the cache. This means thestore may change memory without permission and without taking an abort.If the store did a pre- or post-index update on its address, the register file correctly flushes theupdate. This means that if the store is executed on return from the exception, correct data will bestored into memory at the correct address.Example Manifestations:The following examples explain how the erratum may manifest itself. The examples are intendedto help developers assess the impact upon their applications. Note that this is not an exhaustive list,there may be other examples depending upon how specific application code is architected.a.) Copy on Write -In a multi-tasking OS, a process has read access to a shared memory region, but not write access.Upon a write, the data abort handler will create a physical copy of that region and allow writeaccess to that new region.In the failing case, the shared read-only region could be updated incorrectly and without a dataabort. Eventually, when the original process is returned to, a data abort will happen, but theproblem is that the memory has already been corrupted. Linux supports Copy on Write and ifactivated, could experience the erratum. Other OSes may also be affected.b.) Flags to memory shared with interrupt handler -28 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update