Intel 80200 Processor based on Intel XScale Microarchitecture

Errata18. Store of less than a word length, corrupts data of a previous aborting storeProblem:If there is a store instruction that hits the cache but receives a data TLB abort, and the nextinstruction was another store with a different byte footprint within an aligned 32 bit word (seebelow), the cache data may be modified in some or all of the bytes that would have been written bythe store.The abort will be taken, but the aborted store may partially modify the cache data.This means that a user process may be able to modify up to three bytes of one word in a protectedmemory region before going to the abort handler.If the abort handler removes the cause of the abort and re-executes the aborting instruction withouta fault, the memory location will now be correct with the stored value.If the aborting store is not re-executed:If the aborting store was to a write-through region, only the cached copy of line will be updated.This modified data will never be evicted to external memory. If the abort handler invalidates thatcache line in the cache, memory will now be correct. Invalidating that line is safe because externalmemory has a coherent copy of that data at all times.If the memory region is not write-through, the cache line can be invalidated, but any other data inthat line that has been modified but not updated in external memory will be lost. There is no cleanway for the abort handler to recover the data that was modified by the aborting store.Footprint Cases:Aborting Instruction Next Instruction Resultstr strb, strh failstr str passstrh (efa(1) = 0) strb, strh (efa(1) = 1) failstrh (efa(1) = 0) str, strh (efa(1) = 0) passstrh (efa(1) = 1) strb, strh (efa(1) = 0) failstrh (efa(1) = 1) str, strh (efa(1) = 1) passstrbstrbstrb (different efa(1:0)),strh (different efa(1))str, strh (same efa(1),strb (same efa(1:0))failpassWorkaround:If data aborts are rare in the system and indicate broken user code to be fixed, you may not beaffected by the problem.If you are affected, one workaround is to use write-through memory, and in the data abort handlerfor any store, invalidate the data cache line at the address of the store.Status: Fixed. Fixed on A-1 stepping. See the Table “Summary Table of Changes” on page 7.18 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update