Intel 80200 Processor based on Intel XScale Microarchitecture

Specification ChangesSpecification Changes1. Revised and moved to Specification Clarification 2.2. Drowsy Mode has been De-SpecifiedIssue: Drowsy mode is no longer a low power mode that is supported on the <strong>80200</strong> processor. Use idlemode or sleep mode instead. For drowsy mode references in the <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on<strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual, see documentation change #8. Writing a‘2’ to the PWRMODE register in CP14, register 7, is considered a ‘reserved’ mode and should notbe used.3. New ECC Disable Bit Available on the C-0 and D-0 StepIssue: When using the 80312 companion chip with the <strong>80200</strong> processor, both devices will generate ECCbits for sub-64 bit stores (writes) to SDRAM. Therefore, the <strong>80200</strong> does not need to performRead-Modify-Writes (RMWs) for sub-64 bit stores as this is handled by the 80312 and will impactperformance.A new bit has been defined for the <strong>80200</strong> C-0 and D-0, which disables the RMWs for sub-64 bitstores. Bit 31 in ECTST (register 8, CP13) is now defined as the Disable Write ECC (DWE) bit. IfDWE is written as a '1', even if ECC is enabled, then the <strong>80200</strong> will not perform the usual ECCactions when writing data. In other words, if DWE = '1' and a write is performed to ECC-protectedmemory, the Bus Controller Unit (BCU) will not perform a RMW. The value on the ECC bus(DCB[7:0] signals) in this case will be unpredictable but will be consistent with whatever is beingdriven on D[63:0]. For example, in the case of a non-cacheable DWORD write, D[31:0] is definedby the store instruction and D[63:32] is unpredictable. However, DCB[7:0] is still consistent withwhat is driven out on D[63:0].DWE resets to '0' and is write-only. Reads of DWE result in an unpredictable value. The actionsthat the <strong>80200</strong> perform when reading data are unaffected by the setting of DWE.When DWE is written, it must be done while ECC is disabled in the BCU (BCUCTL.3 = '0').Software should only change the value of DWE once, typically at initialization/reset time.Changing the value of DWE in other circumstances results in unpredictable behavior.The <strong>80200</strong> processor is still responsible for validating ECC on reads, and therefore is required tohave ECC enabled when being used with the 80312 I/O companion chip. This new bit eliminatesthe ECC redundancy on writes.4. 200MHz <strong>Processor</strong> AvailableIssue: On November 12, 2002, <strong>Intel</strong> announced a 200MHz version of the <strong>80200</strong> processor. This productis <strong>based</strong> on the D-0 stepping and is only guaranteed to operate at 200MHz with a voltage of 1.1v+/-5%.At a core frequency of 200MHz, the MCLK is restricted to 66MHz or less. CLK and MCLK areasynchronous clocks, but the internal core frequency must be at least 3x faster than MCLK (seesection 8.1 in the <strong>80200</strong> <strong>Processor</strong> Manual). For example, if the core clock is 200MHz, MCLK isrestricted to 66MHz or less. Therefore, the 80312 I/O companion chip cannot be used with the200MHz processor because it provides an MCLK of 100MHz.The <strong>80200</strong> processor can initialize and operate at 200MHz when CLK = 33MHz, PLLCFG = 1(initial clock multiplier of 6) and MCLK is < or = 66MHz.36 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update