Intel 80200 Processor based on Intel XScale Microarchitecture

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Errata28. Incorrect decode of Unindexed Mode, using Addressing Mode 5, cancorrupt protected registersProblem:Workaround:The instruction decoder incorrectly decodes the valid combination of P=0, U=1 and W=0, whenusing unindexed mode in addressing mode 5 (load and store coprocessor). In this case, the LDC orSTC should produce consecutive address loads or stores, with no base update until the coprocessorsignals that it has received enough data. Instead, the instruction gets separated into an LDR/STRand a CP access.The LDR/STR gets decoded as a post-index address, updating the base register. Due to thedecoding as post-index, the ‘option’ bits, normally reserved for the coprocessor in unindexedmode, will become the 8 bit offset value used in the base register update calculation.The implication is that protected registers can be corrupted. This errata can cause the corruption ofFIQ registers, R13-R14, in user and system modes when the LDC instruction is executed usingunindexed addressing mode. It can also cause the corruption of FIQ registers, R8-R12, in any modewhen the LDC instruction is executed using unindexed addressing. The R13 register in debugmode may also be corrupted during an LDC in any mode. In the case of STC, only Rn is corrupted.Unexpected memory accesses can also occur. In the case of an LDC, any memory location may beaccessed, since the FIQ registers may be improperly used as the base register. In the case of anSTC, the memory word located at Rn+4 will be corrupted. This is the memory locationimmediately following the locations which should be modified by STC unindexed.Do not use unindexed addressing in addressing mode 5 - Load and Store Coprocessor.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.29. Load immediately following a DMM flush entry is also flushedProblem:Workaround:A load that immediately follows a data memory management (DMM) flush entry command, thatalso hits the data TLB, is also flushed. Therefore, the instruction immediately following the flush isalso flushed from the data TLB.All flush entry commands to the data TLB must be followed by 2 nops. The first ensures that theerrata is not encountered, and the second ensures that the speed path is not hit.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.30. Trace Buffer does not operate below 1.3 VProblem:Workaround:The trace buffer within the debug unit is not guaranteed to operate, due to voltage sensitivity, whenthe Vcc voltage supply is below 1.3 V.Make sure the voltage is above 1.3 V during debug.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.22 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update
Errata31. Thumb branch with the Branch Target Buffer enabled, can go to the wrongaddressProblem:Workaround:A mispredicted 'not taken' thumb branch, with the branch target buffer (BTB) enabled, can causeincorrect program flow.Conditions to cause the problem:1. BTB must be enabled2. Thumb mode3. Conditional branch at address XXXX X1FC4. The branch must be predicted as taken, but then is not taken.Branch flush occurs but execution continues from the wrong address, rather than just 'fallingthrough'.Don't run thumb code with the BTB enabled.Status: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.32. Back to back external aborts can cause a hangProblem:Workaround:The following causes a bus hang:1.
Page 1 and 2: Intel ® 8
Page 3 and 4: ContentsRevision History ..........
Page 5 and 6: Revision HistoryscDate Version Desc
Page 7 and 8: Summary Table of ChangesSummary Tab
Page 9 and 10: Summary Table of ChangesErrata (She
Page 11 and 12: Identification InformationIdentific
Page 13 and 14: ErrataErrata1. Branch and Link inst
Page 15 and 16: Errata9. Last abort is missed on re
Page 17 and 18: Errata17. Boundary scan is not full
Page 19 and 20: Errata19. Back to back I/O transact
Page 21: Errata25. Dirty bits are not cleare
Page 25 and 26: Errata36. Incorrect ECC Attribute U
Page 27 and 28: Errata39. CP15 Data Cache Unlock Co
Page 29 and 30: ErrataIf there is a flag used to co
Page 31 and 32: Errata41. Data cache dirty bits may
Page 33 and 34: Errata45. Instruction Memory Manage
Page 35 and 36: Errata48. Disabling and re-enabling
Page 37 and 38: Specification Changes5. Extended Te
Page 39 and 40: Specification ClarificationsSpecifi
Page 41 and 42: Documentation ChangesLOOP1:LOCKLINE
Page 43 and 44: Documentation Changes14. Figure 10-

Intel 80200 Processor based on Intel XScale Microarchitecture

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