Intel 80200 Processor based on Intel XScale Microarchitecture

Errata22. Debug unit synchronization with the TXRXCTRL registerProblem:Workaround:The RX bit in the TXRXCTRL (TX/RX Control) register comes from the JTAG clock domain tothe core clock domain, and several cycles are needed for the register in the core clock domain toupdate. During this time, a debugger which is running a fast JTAG clock, relative to the core clock,may read the bit before it updates in the register, thus reading the old value.The JTAG clock should be slower than the core clock.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.23. Synchronization Request is not asserted when the Data Cache Unit pipe isemptyProblem:Workaround:When the 'Drain Write Buffer' command is issued, the <strong>Intel</strong> <strong>80200</strong> <strong>Processor</strong> should drain anymemory transactions in its own pipe and issue a synchronization request on the external bus. If thedrain command is issued when there are no memory transactions in the <strong>Intel</strong> <strong>80200</strong> <strong>Processor</strong>, thecommand does nothing. The <strong>Intel</strong> <strong>80200</strong> <strong>Processor</strong> recognizes that it is drained and assumes noaction is necessary, therefore no synchronization requests are driven on the external bus.See items #1 and #2 below:1. When a store needs to be drained, perform a load back from that location and introduce adependency.Example: str r2,[r1] ; r1 = memory mapped register, etc.ldr r2,[r1]mov r2,r2 ; nop with dependencyThis stalls the core correctly, but has some performance hit over the drain solution.2. Do any I/O transaction (a memory request to a page with attributes X=C=B=0). The dummyI/O transaction stalls the core until the I/O transaction and all previous transactions havefinished.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.24. Data Cache parity evictionProblem:If a line is evicted from the data cache (most likely by replacement, but possibly by an explicit datacache clean line command), depending on the timing of data returning from the bus, the parity errormay not be reported. The corrupted data may be written to external memory without any abortbeing triggered.This is seen if the following is true:1. There is a parity error in the data cache.2. It is in the first two words of an eight word aligned cache line.3. It is to write back memory.4. The data is dirty (not updated in external memory yet).If there are no parity errors introduced into the array, no problem is seen.Workaround: No workaround.Status: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.20 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update