Intel 80200 Processor based on Intel XScale Microarchitecture

More documents

Recommendations

Info

Specification ChangesThe four layer, no airflow configuration shows a theta ja of 21.01, which is higher than the target of20.83. Even in this scenario the <strong>80200</strong> should be fine, <strong>based</strong> on the fluctuation of the power.Note:This information is given as a reference point only. Customers need to perform thorough thermalsimulations <strong>based</strong> on their specific application. The easiest method is to measure the casetemperature on top of the package to verify that Tcase is below the 105C limit.38 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update
Specification ClarificationsSpecification Clarifications1. TRST# UsageProblem:Here are three different options for TRST# on the <strong>Intel</strong> ® <strong>80200</strong> processor:1. Tie TRST# to ground, if the JTAG port is never be used.2. Tie TRST# to RESET#. TRST# doesn't need to be asserted every time RESET# is asserted,but TRST# does need to be asserted on power-up or else the TAP controller is in an unknownstate. The issue with this option is with an ICE connected to the JTAG port, it needs to be ableto control TRST# independently of RESET# or it looses debug functionality.3. Assert TRST# on power-up and when instructed by an external JTAG/debug controller. Thisgives full debug functionality. See the ‘Recommended JTAG Circuitry for Debug’ applicationnote located at: developer.intel.com/design/iio/applnots/273538.htm, or see your debugger'sdocumentation for special requirements.2. STRD and LDRD InstructionsProblem: STRD (store double-word) and LDRD (load double-word) are new instructions in the ARMArchitecture Specification, v5TE. These load and store instructions can be used to transfer twoadjacent words of memory to or from any of the register pairs.The instruction decoder on the <strong>Intel</strong> ® <strong>80200</strong> processorr divides the STRD instruction into two STRinstructions. This is because the internal (core) data width is 32 bits. When coalescing is turned 'off'(CP15, R1, bit 0 = 1), the core always emits two 32-bit transactions. When coalescing is turned 'on'(CP15, R1, bit 0 = 0), the write buffer may combine them into one 64-bit request.3. Write Coalescing with the <strong>Intel</strong> ® 80312 I/O Companion ChipProblem: The write coalescing feature in the <strong>Intel</strong> ® <strong>80200</strong> processor (<strong>80200</strong>) can be used with the <strong>Intel</strong> ®80312 I/O Companion Chip (80312) to deliver higher memory throughput on core writes to localmemory. Enabling write coalescing may also significantly increase overall applicationperformance. Write coalescing is globally enabled by CP15, CR1, opcode_2=1, bit 0 = 0, andindividually enabled by the MMU page table descriptors using the C, B and X bits.For write coalescing to local memory to work correctly, ECC must be enabled in the <strong>80200</strong> for allpage descriptors that have coalescing enabled. When ECC is enabled, the <strong>80200</strong> always generates64-bit memory writes due to the ECC mechanism for handling partial writes of less than 64-bits tomemory regions. For sub 64-bit writes, the <strong>80200</strong> always generates read-modify-write (RMW) bustransactions, in order to update ECC by merging in the byte lanes from main memory beforewriting the data back out.For steppings of the <strong>80200</strong> that have the Disable Write ECC feature (see Specification Change 3),write coalescing and the enabling of the DWE bit are mutually exclusive when used with the80312. Setting the DWE bit disables the RMW mechanism that allows coalesced writes tocomplete correctly. The disable write ECC feature (DWE bit) should not be used with writecoalescing enabled.With coalescing enabled, writes may occur out of program order to external memory. When theorder of the writes is important, then use fences, since anything that is coalesced can be transferredout of order (see section 3.2.2.6 in the <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual).<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 39
Page 1 and 2: Intel ® 8
Page 3 and 4: ContentsRevision History ..........
Page 5 and 6: Revision HistoryscDate Version Desc
Page 7 and 8: Summary Table of ChangesSummary Tab
Page 9 and 10: Summary Table of ChangesErrata (She
Page 11 and 12: Identification InformationIdentific
Page 13 and 14: ErrataErrata1. Branch and Link inst
Page 15 and 16: Errata9. Last abort is missed on re
Page 17 and 18: Errata17. Boundary scan is not full
Page 19 and 20: Errata19. Back to back I/O transact
Page 21 and 22: Errata25. Dirty bits are not cleare
Page 23 and 24: Errata31. Thumb branch with the Bra
Page 25 and 26: Errata36. Incorrect ECC Attribute U
Page 27 and 28: Errata39. CP15 Data Cache Unlock Co
Page 29 and 30: ErrataIf there is a flag used to co
Page 31 and 32: Errata41. Data cache dirty bits may
Page 33 and 34: Errata45. Instruction Memory Manage
Page 35 and 36: Errata48. Disabling and re-enabling
Page 37: Specification Changes5. Extended Te
Page 41 and 42: Documentation ChangesLOOP1:LOCKLINE
Page 43 and 44: Documentation Changes14. Figure 10-

Intel 80200 Processor based on Intel XScale Microarchitecture

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?