Intel 80200 Processor based on Intel XScale Microarchitecture

Errata34. Aborted Store that Hits the Data Cache May Mark Write-Back Data as DirtyProblem:Workaround:When there is an aborted store that hits clean data in the data cache (data in an aligned four wordrange that has not been modified from the core since it was last loaded in from memory or cleaned),the data in the array is not modified (the store is blocked), but the dirty bit is set.When the line is then aged out of the data cache or explicitly cleaned, the data in that four wordrange is evicted to external memory, even though it has never been changed. In normal operationthis is nothing more than an extra store on the bus that writes the same data to memory that isalready there.Here is the boundary condition where this might be visible:1. A cache line is loaded into the cache at address A.2. Another master externally modifies address A.3. A core store instruction attempts to modify A, hits the cache, aborts because of MMUpermissions, and is backed out of the cache. That line normally is not marked dirty, butbecause of this errata is marked as dirty.4. The cache line at A then ages out or is explicitly cleaned. The original data from location Awill be evicted to external memory, overwriting the data written by the external master.This only happens when software is allowing an external master to modify memory that is,write-back or write-allocate in the <strong>80200</strong> page tables, and depending on the fact that the data is not'dirty' in the <strong>80200</strong> cache, to preclude the cached version from overwriting the external memoryversion. When there are any semaphores or any other handshaking to prevent collisions on sharedmemory, this is not a problem.For this shared memory region, mark it as write-through memory in the <strong>80200</strong> page table. Thisprevents the data from ever being written out as dirty.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.35. Data Cache Unit Signals Incorrect Number of Misses or Memory Operationsto the Performance Monitoring UnitProblem:Workaround:Under certain conditions inside the Data Cache Unit pipeline, the DCU can allow an operation tomove from the D2 pipe stage to the D3 pipe stage without the deassertion of D2 stall. The operationthat does this is not properly signaled to the Performance Monitoring Unit and therefore the PMUcount of cache misses and memory operations can be lower than expected.No workaround.Status: Fixed. Fixed on C-step. See the Table “Summary Table of Changes” on page 7.24 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update