Intel 80200 Processor based on Intel XScale Microarchitecture

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Identification InformationDie Details (Sheet 2 of 2)Part NumberSteppingQDF/SpecificationNumberVoltage(V)<strong>Intel</strong> ®<strong>80200</strong><strong>Processor</strong>Speed(MHz)NotesFW<strong>80200</strong>M600FW<strong>80200</strong>M733FW<strong>80200</strong>M200FW<strong>80200</strong>M400FW<strong>80200</strong>M600FW<strong>80200</strong>M733FW<strong>80200</strong>M200TFW<strong>80200</strong>M400TFW<strong>80200</strong>M600TFW<strong>80200</strong>M733TD-0D-0D-0D-0D-0D-0D-0D-0D-0D-0Q367Q368SL6WLSL676SL677SL678SL6WMSL6WNSL6WPSL6WQ1.51.51.11.31.51.51.11.31.51.5up to 600up to 733up to 200up to 400up to 600up to 733up to 200up to 400up to 600up to 733General SamplesGeneral SamplesProduction MaterialProduction MaterialProduction MaterialProduction MaterialExt Temp. Prod. MaterialExt Temp. Prod. MaterialExt Temp. Prod. MaterialExt Temp. Prod. MaterialDevice ID RegistersDevice andStepping<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture(ARM* architecture compliant)Device ID (CP15, Register0 - opcode_2=0)JTAG Device IDA-0 0x69052000 0x09263013A-1 0x69052001 0x19263013B-0 0x69052002 0x29263013C-0 0x69052003 0x39263013D-0 0x69052004 0x4926301312 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update
ErrataErrata1. Branch and Link instruction does not branch after Branch Target Buffer(BTB) invalidateProblem:A branch and link (BL) instruction after a BTB invalidate can branch to the wrong address. Thiscould result in incorrect software operation. The BTB invalidate can happen with a CP15 register 7function, a write to the Process ID register, or when the instruction cache is invalidated via CP15register 7 function.Workaround: Flush the execution pipeline after code that invalidates the BTB. For example, the followinginstruction does this:SUB PC, PC, #4 ;flush the pipeStatus: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.2. Multiple ECC errors reported on a single transactionProblem:Workaround:A multi-bit ECC error is logged on more than one 64-bit bus cycle of a cache line fill. In somesituations (specifically when a store is issued soon after the cache line fill), the bus controlleridentifies an extra error back to the core. The effect is that multiple data aborts are taken. The extraabort occurs soon after the real abort (before the link register of the first abort is saved off). Theeffect is to lose the original link register. This can be identified by detecting when the link registerpoints to the beginning of the data abort handler and that only one error is logged in the buscontroller registers.Software can detect the situation if it occurs, but recovery may be impossible. Systems have littlealternative other than logging the error and returning back to a stable state, which may entail asystem restart.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.3. Performance Monitor Control Register (PMCR) needs an extra write oninitial enable of branch countProblem:Workaround:When first enabling the counting of event 0x5, branch instruction executed, the PerformanceMonitoring Unit can incorrectly count a branch that never occurs.Write the PMCR register twice. The first time the Counter Rest bit is set and the Enable bit is a“don’t care”. The second time, both the Counter Reset and Enable bits must be set.Status: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.4. Invalidates and cleans of the Translation Look-aside Buffer (TLB) andcache, will PIDify the addressProblem:Workaround:When invalidating of cleaning a TLB or cache entry, the address is getting ORed by the ProcessID. This issue only occurs when the first 7 bits of the address are zero and the Process ID is ineffect.Always supply a Modified Virtual Address (MVA) to these functions, or disable the PID byzeroing it before performing these operation.Status: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 13
Page 1 and 2: Intel ® 8
Page 3 and 4: ContentsRevision History ..........
Page 5 and 6: Revision HistoryscDate Version Desc
Page 7 and 8: Summary Table of ChangesSummary Tab
Page 9 and 10: Summary Table of ChangesErrata (She
Page 11: Identification InformationIdentific
Page 15 and 16: Errata9. Last abort is missed on re
Page 17 and 18: Errata17. Boundary scan is not full
Page 19 and 20: Errata19. Back to back I/O transact
Page 21 and 22: Errata25. Dirty bits are not cleare
Page 23 and 24: Errata31. Thumb branch with the Bra
Page 25 and 26: Errata36. Incorrect ECC Attribute U
Page 27 and 28: Errata39. CP15 Data Cache Unlock Co
Page 29 and 30: ErrataIf there is a flag used to co
Page 31 and 32: Errata41. Data cache dirty bits may
Page 33 and 34: Errata45. Instruction Memory Manage
Page 35 and 36: Errata48. Disabling and re-enabling
Page 37 and 38: Specification Changes5. Extended Te
Page 39 and 40: Specification ClarificationsSpecifi
Page 41 and 42: Documentation ChangesLOOP1:LOCKLINE
Page 43 and 44: Documentation Changes14. Figure 10-

Intel 80200 Processor based on Intel XScale Microarchitecture

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