Intel 80200 Processor based on Intel XScale Microarchitecture

More documents

Recommendations

Info

Erratainterrupt between any of the instructions in the critical code region may cause an errorcondition. Modifying a semaphore is a typical critical code example.3. Use the atomic instructions, SWP or SWPB. Therefore, limiting the manipulation of sensitivevariables to these instructions will avoid the erratum.c.) Debug / Breakpoints -Most debug handlers flush the cache when a break occurs, which reduces the potential for a cacheeviction and reduces the potential for a system to be affected by the erratum. So there are few timesthis erratum should be seen in a debug session, and misinterpreting an apparent bug may beavoided by knowing where this erratum might occur.Status: Fixed. Fixed on D-step. See the Table “Summary Table of Changes” on page 7.30 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update
Errata41. Data cache dirty bits may be corrupted if a line invalidate is followedimmediately by a storeProblem: The dirty bits in the data cache can be corrupted by an Invalidate Data Cache Line command toaddress “A” immediately followed by any store to address “B” where address “B” and address “A”are to the same cache set (bits 9:5 of the two addresses are the same).This can lead to clean or invalid data being marked dirty in the cache, or dirty data in the cachebeing marked clean. Possible outcomes:1. Invalid data being marked dirty can lead to unpredictable four word stores to an unpredictableaddress in memory.2. Valid, but clean write-back data, being marked dirty can lead to unnecessary evictions toexternal memory.3. Valid dirty data being marked clean can lead to data corruption. External memory will not beupdated upon cache line replacement.Workaround: Do not perform a store operation immediately following an Invalidate Data Cache Line command.Invalidate Data Cache Line is a supervisor mode instruction. Placing a NOP between these twooperations will avoid the erratum.Status: Fixed. Fixed on D-step. See the Table “Summary Table of Changes” on page 7.42. Data cache dirty bits may be corrupted if a bus error on a cache line fill isfollowed immediately by a storeProblem: This erratum is very similar to erratum #41. The problem is the same, but the root cause isdifferent. If certain types of bus errors occur, and a store to the cache occurs near the time when theerror is reported, the dirty bits in the array in the same set as the store may be corrupted. The buserrors that can cause this erratum are a multi-bit ECC error on a returning cache line fill orassertion of the external ABORT pin on a returning cache line fill.This can lead to clean or invalid data being marked dirty in the cache, or dirty data in the cachebeing marked clean. Possible outcomes:1. Invalid data being marked dirty can lead to unpredictable four word stores to an unpredictableaddress in memory.2. Valid, but clean write-back data, being marked dirty can lead to unnecessary evictions toexternal memory.3. Valid dirty write-back data being marked clean can lead to data corruption. External memorywill not be updated upon cache line replacement.Bus errors reported on any store, or on loads that are smaller than 32 bytes will not cause this bug.Workaround: Set up the page tables such that unimplemented regions of memory do not have valid page tableentries. A precise data abort will occur on accesses to those regions and no bus error will be seen.Any region of memory that has valid memory locations and unimplemented memory locationswithin one page should be marked non-cacheable to avoid cache line fills. This will preclude theerratum. An example of this might be a memory mapped register region.Any region of memory that may generate bus aborts that cannot be prevented by appropriate pagetable entries should be marked non-cacheable.If there is some reason that code must do a cache line fill that will have a chance of creating a busabort, then avoid store instructions in supervisor mode while potentially aborting cache line fillsare pending. The drain write buffer CP15 command issued right after the cache line fill can be usedto stall the core during these transactions.For any triggering abort that cannot be avoided by page table permissions or cacheability (such asmulti-bit ECC error on a cache line fill), there is no known workaround. Bus aborts should, ingeneral, be avoided during normal operation.Status: Fixed. Fixed on D-step. See the Table “Summary Table of Changes” on page 7.<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 31
Page 1 and 2: Intel ® 8
Page 3 and 4: ContentsRevision History ..........
Page 5 and 6: Revision HistoryscDate Version Desc
Page 7 and 8: Summary Table of ChangesSummary Tab
Page 9 and 10: Summary Table of ChangesErrata (She
Page 11 and 12: Identification InformationIdentific
Page 13 and 14: ErrataErrata1. Branch and Link inst
Page 15 and 16: Errata9. Last abort is missed on re
Page 17 and 18: Errata17. Boundary scan is not full
Page 19 and 20: Errata19. Back to back I/O transact
Page 21 and 22: Errata25. Dirty bits are not cleare
Page 23 and 24: Errata31. Thumb branch with the Bra
Page 25 and 26: Errata36. Incorrect ECC Attribute U
Page 27 and 28: Errata39. CP15 Data Cache Unlock Co
Page 29: ErrataIf there is a flag used to co
Page 33 and 34: Errata45. Instruction Memory Manage
Page 35 and 36: Errata48. Disabling and re-enabling
Page 37 and 38: Specification Changes5. Extended Te
Page 39 and 40: Specification ClarificationsSpecifi
Page 41 and 42: Documentation ChangesLOOP1:LOCKLINE
Page 43 and 44: Documentation Changes14. Figure 10-

Intel 80200 Processor based on Intel XScale Microarchitecture

Create successful ePaper yourself

Delete template?

Save as template?