Intel 80200 Processor based on Intel XScale Microarchitecture

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Documentation Changes8. All References to Drowsy Mode should be Removed from the <strong>80200</strong>Developer’s ManualIssue: Drowsy Mode has been de-specified (See specification change #2).The following Drowsy Mode references in the <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manuall should be removed:• Figure 1-1 on page 1-2• Section 1.1.2.6 on page 1-4• Table 7-23 on page 7-19 (2 = ‘reserved’)• Table 7-24 on page 7-19• Introduction section of page 8-1• All sections and figures on pages 8-5 and 8-6.Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual.9. Table 11-6 on page 11-10 has a new bit function for ECTST.31Issue:Bit 31 in the ECTST register is no longer Reserved. ECTST.31 is now defined as Disable WriteECC (DWE). See specification change 3 for more details.Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual.10. Figure C-2 on page C-7 shows an incorrect stateIssue:The initial TRST# state does not belong in this state diagram. It should be shown instead as'TRST# = 0'. A correct version can be seen in Figure 14-2 of the <strong>Intel</strong> ® 80312 I/O Companion ChipDeveloper’s Manual.Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual.11. Example code is incorrect on page 13-15Issue:The first instruction in the example code, at the bottom of page 13-15, should be changed from‘mcr’ to ‘mrc’ (loop: mrc p14, 0, r15, c14, c0, 0).Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual(273411).12. Example code is incorrect on page 13-45Issue: The third instruction in the loop routine should change ‘c8’ to ‘c9’ (mrc p14, 0, r0, c9, c0, 0).Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual(273411).13. Number of clocks is incorrect on page 8-2Problem: On page 8-2, the last sentence of the second paragraph, change ‘approximately one thousand CLKcycles’ to ‘approximately two thousand CLK cycles’.It should read as: “If there are no external bus transactions, this procedure takes approximately twothousand CLK cycles, the same time it takes to transition out of reset.”Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual(273411).42 <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update
Documentation Changes14. Figure 10-12 on page 10-22 shows incorrect BE# valueProblem:The BE# value in Figure 10-12 is incorrect. Change from ‘0x00’ to ‘0xF0’ to indicate 4 bytes, asused in the example.Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual(273411).15. Example code is incorrect on page 7-17Problem: Example 7-1 on pg 7-17 reads:LDR R0, =0x3FFE ; bit 0 is clearIt should read:LDR R0, =0x0000 ; bit 0 is clearorMOV R0, #0x00 ; bit 0 is clearThis conflicts with the statement made at the bottom of table 7-20, "Setting any of bits 12:1 has anundefined effect."Affected Docs: <strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Developer’s Manual(273411).<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 43
Page 1 and 2: Intel ® 8
Page 3 and 4: ContentsRevision History ..........
Page 5 and 6: Revision HistoryscDate Version Desc
Page 7 and 8: Summary Table of ChangesSummary Tab
Page 9 and 10: Summary Table of ChangesErrata (She
Page 11 and 12: Identification InformationIdentific
Page 13 and 14: ErrataErrata1. Branch and Link inst
Page 15 and 16: Errata9. Last abort is missed on re
Page 17 and 18: Errata17. Boundary scan is not full
Page 19 and 20: Errata19. Back to back I/O transact
Page 21 and 22: Errata25. Dirty bits are not cleare
Page 23 and 24: Errata31. Thumb branch with the Bra
Page 25 and 26: Errata36. Incorrect ECC Attribute U
Page 27 and 28: Errata39. CP15 Data Cache Unlock Co
Page 29 and 30: ErrataIf there is a flag used to co
Page 31 and 32: Errata41. Data cache dirty bits may
Page 33 and 34: Errata45. Instruction Memory Manage
Page 35 and 36: Errata48. Disabling and re-enabling
Page 37 and 38: Specification Changes5. Extended Te
Page 39 and 40: Specification ClarificationsSpecifi
Page 41: Documentation ChangesLOOP1:LOCKLINE

Intel 80200 Processor based on Intel XScale Microarchitecture

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