Intel 80200 Processor based on Intel XScale Microarchitecture

ErrataErrata1. Branch and Link instruction does not branch after Branch Target Buffer(BTB) invalidateProblem:A branch and link (BL) instruction after a BTB invalidate can branch to the wrong address. Thiscould result in incorrect software operation. The BTB invalidate can happen with a CP15 register 7function, a write to the Process ID register, or when the instruction cache is invalidated via CP15register 7 function.Workaround: Flush the execution pipeline after code that invalidates the BTB. For example, the followinginstruction does this:SUB PC, PC, #4 ;flush the pipeStatus: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.2. Multiple ECC errors reported on a single transactionProblem:Workaround:A multi-bit ECC error is logged on more than one 64-bit bus cycle of a cache line fill. In somesituations (specifically when a store is issued soon after the cache line fill), the bus controlleridentifies an extra error back to the core. The effect is that multiple data aborts are taken. The extraabort occurs soon after the real abort (before the link register of the first abort is saved off). Theeffect is to lose the original link register. This can be identified by detecting when the link registerpoints to the beginning of the data abort handler and that only one error is logged in the buscontroller registers.Software can detect the situation if it occurs, but recovery may be impossible. Systems have littlealternative other than logging the error and returning back to a stable state, which may entail asystem restart.Status: NoFix. Will not be fixed on D-step. See the Table “Summary Table of Changes” on page 7.3. Performance Monitor Control Register (PMCR) needs an extra write oninitial enable of branch countProblem:Workaround:When first enabling the counting of event 0x5, branch instruction executed, the PerformanceMonitoring Unit can incorrectly count a branch that never occurs.Write the PMCR register twice. The first time the Counter Rest bit is set and the Enable bit is a“don’t care”. The second time, both the Counter Reset and Enable bits must be set.Status: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.4. Invalidates and cleans of the Translation Look-aside Buffer (TLB) andcache, will PIDify the addressProblem:Workaround:When invalidating of cleaning a TLB or cache entry, the address is getting ORed by the ProcessID. This issue only occurs when the first 7 bits of the address are zero and the Process ID is ineffect.Always supply a Modified Virtual Address (MVA) to these functions, or disable the PID byzeroing it before performing these operation.Status: Fixed. Fixed on B-step. See the Table “Summary Table of Changes” on page 7.<strong>Intel</strong> ® <strong>80200</strong> <strong>Processor</strong> <strong>based</strong> on <strong>Intel</strong> ® XScale Microarchitecture Specification Update 13