Advanced Micro Devices - FTP

CHAPTER 1Overviewany execution process can access the CPU's total addressspace--4 Gbytes for the 68020.Direct addressing is preferred when the 68020 controlsperipheral devices or when the peripherals have uniqueaddresses because only one user can access the quad pixeldata-flow manager in an interactive graphics system.Even if this user displays results from a multitasking process,the I/O accesses run sequentially through an operatingsystem driver. Ideally, a PAL device contains the addressdecoding logic needed to generate the relevant ChipEnable signals to the graphics processor. As a result, thefollowing discussion assumes a direct-addressingscheme.To interface a processor to a peripheral with an independentsystem bus cycle, as the graphics processor has,several control and response signals must be translated.Also, each device must operate at its own highest clockrate, and therefore, asynchronously.The interface to the Am95C60 includes a 16-bit bidirectional,three-state data bus (lines Do to DIs), Read andWrite strobe inputs (RD and WR), a Chip Select input(CS), two address line inputs (Ao and AI)' an interruptoutput, three DMA handshake signals, an output that enablesan external driver, a reset, and a system clock input.The system clock, which runs at up to 20 MHz, times theinternal microengine and controls the display-memorytiming, but not the system-bus and video timing. The twoaddress lines connect to four ports within the device.A typical application has a 68020 connected to twoAm95C60s that form an eight-plane system (Fig. 2). APAL device decodes the 68020 address and outputs twoChip Select (CSo and CSI) signals to the graphics processors.A third signal, CSQPDM, which shows an access toeither graphics processor, combines with the 68020'sReadIWrite signal to form the read and write inputs forthe Am95C60. The timing of the Chip Select signal andthe read and write inputs follows the timing of the 68020'sSystem busRedGreenBlueColorpalette1. The AM95C60 Quad Pixel Datal/ow Manager can accommodate four bitmappedmemory planes. A graphics subsystem can include up to 64 devices,for 256 memory planes.Address Strobe, with the addition of the decode logic'Spropagation delay.Because all resources within the graphics processor are16 bits wide, any write cycle to the device results in the 16-bit quantity on the bus being loaded into the appropriateregister. But the data word must be aligned, because theleast significant address line is not used in addressing theresources within the device. Connecting the 68020's addresslines, Al and A2, to the graphics processor's addresspins, Ao and AI> allows data to be transferred one word ata time. Consequently, the quad pixel data-flow managerdoes not need any transfer-size information; the requested16 bits are always fulfilled. The 68020's address bits Aland A2 connect to the graphics processor's two addressinputs, Ao and AI' to select the internal resource for a busaccess.Depending on the speed difference between the twoprocessors, none, one, or more wait states extend the processor'sbus cycle. Two lines-Data Transfer and SizeAcknowledge (DSACK)-