Advanced Micro Devices - FTP

CHAPTER 2System Bus InterfacesEaUENCERSTATECLOCK(60ns)~ (MY~) -------------, L-______________________ ~_J(Sy~)~ --------------------, L.... ________________....INOTE 2AS L--f~N~OT~E~1 ________________________ ~WRBuS ==::::xX'-____________ _~ ------------------------iL ______ ~r----------------------~ ------------------------lL ______________ ~NOTE 1: This delay is dependent on the Address Decode Logic.NOTE 2: This delay in clearing the signal depends on the AddressDecode PAL propagation delay from AS negating.Critical Timing ParametersMin WRQPDM widthSet up CSQPDM to RDQPDM WRQPDM assertingSet up Write Data to WRQPDM negatingRead Data valid from DSACKxx assertingDSACKxx asserting with respect to negative clock edgeRequired70/90/100 nso ns50175/100 ns60 ns max18.5 nsGuaranteed120 ns60 ns>180 ns-401-20/0 ns12 nsWhere more than one figure appears in a column, the different requirements for different speeds (12, 16 and20 MHz) of the Am95C60 are reflected. The MC68020 timing requirements are for a 16.67 MHz device. Referto the Am95C60 Technical Manual and the MC68020 specifications for bus cycle timing details.Figure 2.3-6 Bus Cycle Timing DiagramResponding to a Bus CycleHaving initiated a busy cycle to the Am95C60, logic isrequired to generate sufficient WAIT states to theMC68020 to generate a bus cycle of acceptable length tothe Am95C60. The response lines needing to be set arethe DSACKO and DSACK1 lines. When not asserted,these lines cause WAIT states to be inserted in the buscycle. At the appropriate times, these lines can beasserted, and the code supplied to the MC68020 indicatingthe width of the device responding to the bus cycle (1,2 or 4 bytes wide). The Am95C60 is capable of operatingas either an 8- bit or 16-bit wide port, but in this instance,for optimum performance it should be configured as a 16-bit port and hence should respond with a code of 01 H.(See Figure 2.3-7)DSACK1HHLLDSACKOHLHLFunctionInsert WAIT statesCycle complete - S-bit wide data portCycle complete - 16-bit wide data portCycle complete - 32-bit wide data portFigure 2.3-7 DSACK Code Definition2-38