Advanced Micro Devices - FTP

CHAPTER 2System Bus InterfaceData is sampled on the next negative edge of the 68020 clock after DSACK isasserted (in the synchronous case), i.e., at the end of state 3. The data willbe held stable by the QPDM well beyond this point under the control of RDQPDMnegating, and hence lIElets the Data Hold tillEl requirel!Elnts of the 68020 (0 ns inthe synchronous mode)."/RDQPDM = CSQPDM * /WRBUS * (STATE 1 + STATE2 + STATE 3 + STATE4);END.Listing sum-of-products equations for QPDM_68020_INTERFACE_CONTROLLER/COUNT[2]/COUNT[l]/COUNT[O]/QPDMEN/DSACKl/WRQPDM/RDQPDM:- /COUNT[1]*COUNT[2]*AS+ COUNT[0]*COUNT[1]*/COUNT[2]+ /COUNT[0]*/COUNT[1]*COUNT[2];:- COUNT[0]*/COUNT[1}*/COUNT[2]+ /COUNT[0]*COUNT[1]*/COUNT[2];:= /COUNT[1]*COUNT[2]*AS+ /COUNT[0]*COUNT[1]*/COUNT[2]+ /COUNT[0]*/COUNT[1]*COUNT[2]+ /COUNT[O]*/COUNT[l]*AS*CSPLANE+ /COUNT[O]*/COUNT[l]*AS*CSPlXEL+ /COUNT[O]*/COUNT[l]*AS*CSQPDM;= AS*CSPlXEL+ AS*CSPLANE+ AS*CSQPDM;:= COUNT[1]*/COUNT[2];- CSQPDM*WRBUS*COUNT[0]*/COUNT[1]*/COUNT[2]= CSQPDM+WRBUS*/COUNT[0]*COUNT[1]*/COUNT[2];- CSQPDM*/WRBUS*COUNT[0]*/COUNT[2]= CSQPDM*/WRBUS*COUNT[1]*/COUNT[2]+ CSQPDM*/WRBUS*/COUNT[0]*/COUNT[1]*COUNT[2];2-56--