Advanced Micro Devices - FTP

CHAPTER 2System Bus Interfacethat caused the bus cycle to terminate unsuccessfully,such as "Bring in new data from secondary memory orbacking store into local memory".Bus error may be set for other reasons than page fault(the page of memory required is not currently resident inavailable local memory) such as memory parity error oraccess protection violation. In general, the pager mechanismwill be responsible for detecting these exceptionconditions and will normally contain the logic to generatethese signals.A special case of when Bus Error can be set is when anInterrupt Acknowledge cycle is generated by theMC68020 but no device is requesting service. If thiscondition occurs and the Bus Error is asserted in such anInterrupt Acknowledge bus cycle, it is interpreted thatSpurious Interrupt has occurred. The Bus Error exceptionis not taken under this condition. The InterruptHandling logic of Figure 2.3-11 further describes thiscondition.In general, when accessing hardware resources within adevice such as the Am95C60 where the resource shouldalways be available, there should never be a need tounsuccessfully terminate the bus cycle, and hence additionallogic should not be required beyond what is includedin Figure 2.3-11 or would already be presentwithin such a pager system.If a particular system requires that Bus Error or Halt bedriven under specific conditions, itwould be a simple taskto generate control logic to set these signals as appropriate.(See Figure 2.3-6)2.3.6 System Bus ArbitrationThe Am95C60 can only act as a bus slave, never as a busmaster, and hence does not have direct involvement withsystem bus arbitration to become the bus master.However, the task of loading the Am95C60 with data andinstructions can be taken from the host processor andgiven to a suitable DMA controller to reduce the load onthe CPU, thus resulting in greater system performance.Such a DMA controller must interface to the bus arbitrationscheme.2.3.7 Initializing the Am95C60Two main tasks are involved in controlling the Am95C60.In order to initiate any activity within the graphics enginefollowing power-up reset, the device needs to be initializedwith a number of parameters defining the environmentin which it resides (such as the size of the VideoDRAMs constituting the display memory, whether an 8-or 16-bit bus interface is being used to the system bus,etc.). As stated previously, it is essential that eachAm95C60 within a system can individually be chip selectedwhen executing the Set QPDM Position instruction.Once having loaded each Am95C60 position register,most accesses to the array of Am95C60s shouldset all chip select lines (CSQPDM(O ... N), where there areN devices within the system) as all Am95C60s executethe same instruction simultaneously.Execution of these instruction may have different effectson different display memory planes. This depends on thedata already present in display memory or on the contentsof certain registers within each Am95C60. Thefollowing are some examples: defining which planes areactive (activity bits), what color lines should be drawnwhen executing drawing instructions (color bits), whatcolor is being searched for and on which planes, andwhen using Area Fill instructions (color search bits andlisten bits).When the appropriate instruction is used to set thedesired value in these registers, the instruction has withinit a field defining which Am95C60 is being accessed.Each Am95C60 compares this field with the contents ofits plane position register to determine whether it is thetarget for this operation. See Section 13.2.4 of theTechnical Manual.Hence when defining the addresses with the hardwarespace for the Am95C60s within a system, individualaddresses should be allocated for each Am95C60 foruse when initializing the devices. A further addressshould also be allocated causing all CSQPDM(O- N) linesto be asserted for use when accessing all Am95C60ssimultaneously (once all the Am95C60s are initialized).Refer to Figures 2.3-3 and 2.3-4.Once the CPU has initialized the Am95C60, the device isready to begin executing drawing or data manipulationinstructions. Over fifty different instructions are availablewhich can be loaded into the Am95C60 in a number ofdifferent ways.2.3.8 Initiating Am95C60 ActivityLoading Instructions from the Host ProcessorThe most straightforward method of loading instructionsis for the host processor to generate a Write cycle anddirectly address the Instruction FIFO within theAm95C60 by writing to Port 0 in "hardware space" (seeFigure 2.3-8). This method is commonly known asProgrammed 1/0.When servicing the Instruction FIFO by the host processor,the FREQ signal may not be directly connected.However, when this is true, the FREQI interrupt, i.e., theInstruction FIFO is half empty, can be "mask-controlled"2-40