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CHAPTER 3Display Memory BusQPDM) as in the read cycle. The CAS signal stays activefor 80 ns (parameter #57 tw of the QPDM).During the first half of the write cycle the write mask maybe strobed into the video memory chips. A write mask, i.e.the data on the DM(3:0)(15:0) bus, is loaded into thevideo memory chips whenever its write input is LOWduring the falling edge of RAS. If WE is HIGH when RASfalls, all four bits will be written.The WE(3:0) signal is stable 11 ns (parameter #59 ts ofthe QPDM) before the falling edge of RAS and remainsstable for approximately 60 ns (interpolation of theQPDM spec) after the falling edge of RAS. The WE(3:0)signals run through an Am29827 A driver with a best andworst case propagation delay of 3 ns to 13 ns, respectively(interpolation of Am29827A timing specification).Figure 3.1-6 shows thatthis leaves a set-up and hold timefor the write enable pulse Won the video memory chip of2 ns and more than 51 ns respectively, which is easilyfulfilled by video memory chips.The data is supplied to the memory chips without passingthrough any driver. The QPDM provides valid output dataat least 2 ns (parameter #62 ts of the QPDM) prior and60 ns (parameter #63 tH of the QPDM) after the fallingedge of RAS. Figure 3.1-6 shows that this leaves a setupand hold time for the write mask data on the videomemory chips of 6 ns and 48 ns respectively, which iseasily fulfilled by video memory chips.During the second half of the write cycle the actual dataget strobed into the memory chips. The QPDM assertsthe write command at least 13 ns (parameter #60 ts of theQPDM) prior to the falling edge of CAS and has a validWE(3:0) pulse width of at least 78 ns (parameter #61 twof the QPDM). The propagation delay from CAS toCAS*(7:0) is 3 ns to 10 ns. The video memory chips seea write command set-up and hold time of 3 ns and morethan 50 ns, respectively, which satisfies video memorychips.The actual data is output at least 2 ns (parameter #64 tsof the QPDM) prior to the falling edge of CAS and stayvalid at least 60 ns (parameter #65 tH of the QPDM) afterthis falling edge. Figure 3.1-6 shows that this leaves aset-up and hold time for the data on the video memorychip of 5 ns and 50 ns respectively, which again issatisfied by video memory chips.Display Memory Transfer CycleThe timing of the display memory transfer cycle involvesboth the display memory and the VDAFs.The strobing of the row and shifter start address (columnaddress in the read cycle) into the video memory chipsworks with the same timing as in the read cycle. Thus allset-up and hold times for the row, column, and bankselectaddress are fulfilled.During a transfer cycle, however, the XF/G signal is validbefore the falling edge of RAS. The QPDM outputs theXF/G signal 12 ns (parameter #49 ts of the QPDM) beforethe falling edge of RAS. It stays active 140 ns (parameter#69 tp of the QPDM) after the falling edge of RAS and55 ns pparameter #67 tpD of the QPDM) after the fallingedge of CAS. The XF/G Signal becomes inactive at least39 ns (parameter #70 tH of the QPDM) before the risingedge of RAS and at least 40 ns (parameter #68 tll of theQPDM) before the rising edge of CAS. The XF/Gsignalpasses through an Am29827 A buffer, and XF/G* isavailable 3 ns to 16 ns later on the video memory chips.Figure 3.1-7 shows that this leaves (with the propagationdelay from the RAS to the RASbk*(3 :0) signal) a set-upand hold time forthe XF/G Signal with respect to the RASsignal on the video memory chips of 0 ns and 131 ns,respectively. This parameter, again, is fulfilled by videomemory chips.The WE(3:0) signal of the QPDM is HIGH during thecomplete transfer cycle. This indicates a transfer directionfrom the memory array to the shifter. Since this isalways the case, so-called "dummy" transfer cycles arenever required.The falling edge of the RAS signal clocks the flip-flopF114 that generates the transfer signal XFER. Theinverter F04 delays the XF/G signal by 2 ns to 6 ns (F04data). This leaves a set-up and hold time for the XF/Gsignal on the flip-flops F114 of 6 ns and more than 100 nsrespectively, which is more than the required 5 ns and 0ns (F114 data). The propagation delay within the flip-flopis 2 ns to 8 ns (F114 data). The XFER pulse is deactivated2 ns to 8 ns after the rising edge of RAS.The rising edge of the XFER pulse clocks the F74 Dregister to store the bank-select address for the timebetween two transfer cycles. This address is valid 15 ns(parameter #30 ts of the QPDM) before and more than130 ns afterthe falling edge of RAS. This leaves a set-upand hold time with respect to the address for the F74 of17 ns and more than 118 ns, respectively, which is morethan the required 3 ns and 1 ns (F74 data). The propagationdelay forthe ADDR(9:8) signal through the flip-flop is3 ns to 11 ns (F74 data).During a transfer cycle start offset control information isstrobed into the VDAFs. These control data is presentedto the VDAFs on the ACD inputs and are strobed intothe VDAFs by their SBSTR~ inputs. The control data istransferred without buffering from the QPDM CDAT -0outputs to the fourVDAFs. The strobe signal isthe XFERsignal generated by the flip-flop F114. The data on3-11
CHAPTER 3Display Memory Bus~----=!!!.=H~~t;;~;., ................ ........................................................ ~ ... ~65n1-.5&10~ 'L'I>131,.XFER>13OnaAOIJR(9:8)>118n8ACORI(9:8)COAT(2:O)latched--bank telecI addreu stays valkf WIIII..t ...... cyde57reeOnsVSTB16 ..----......
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Am95C60Quad Pixel Dataflow ManagerA
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Authors:Tom CrawfordStuart TindallE
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Table of ContentsCHAPTER 1 Overview
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CHAPTER 1OverviewDESIGN APPLICATION
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and the information is read in on t
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CHAPTER 1Overviewservice. As with t
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CHAPTER 2System Bus Interface2.1 Am
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CHAPTER 2System Bus InterfaceT4 1W
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CHAPTER 2System Bus InterfaceALE ~t
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CHAPTER 2System Bus InterfaceDMAQPD
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CHAPTER 2System Bus Interfacevee20
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CHAPTER 2System Bus InterfaceMATOUT
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CHAPTER 2System Bus InterfaceQPDM i
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CHAPTER 2System Bus InterfaceJ01501
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CHAPTER 2System Bus Interfacedresse
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Page 55 and 56: CHAPTER 2System Bus InterfacesEaUEN
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Page 67 and 68: CHAPTER 2System Bus InterfaceAPPEND
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Page 76 and 77: CHAPTER 3Display Memory BusIn this
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Page 82 and 83: CHAPTER 3Display Memory BusFurtherm
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Page 116 and 117: CHAPTER 3Display Memory BusKANJI RO
Page 118 and 119: CHAPTER 3Display Memory BusTable 3.
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Page 122: CHAPTER 4Video Bus4.1 VIDEO BUS4.2
Page 125 and 126: CHAPTER 4Video Bus4.2.2 High-speed
Page 127 and 128: CHAPTER 4Video BusScan Line End Con
Page 129 and 130: CHAPTER 4Video BusFIFO (VDAF). The
Page 131 and 132: CHAPTER 4Video BusParameter min typ
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CHAPTER 5Evaluation and Demonstrati
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CHAPTERSEvaluation and Demonstratio
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CHAPTER 5Evaluatuion and Demonstrat
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CHAPTER 6Articles/Application Notes
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CHAPTER 6Software10 'This programs
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CHAPTER 6Software950 RETURN960 '970
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CHAPTER 6Software6.2 COPY BLOCK OPE
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CHAPTER 6Software6.2.4 Transparency
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CHAPTER 6Softwarecpy 11 a [temp2] [
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CHAPTER 6Softwarecpy 11 a [temp2] [
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CHAPTER 6SoftwareADDTEMPblk [blksiz
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CHAPTER 6SoftWareSUBSTEMPblk [blksi
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NOTES
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NOTES
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NOTES
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ADVANCED MICRO DEVICES' NORTH AMERI
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