Advanced Micro Devices - FTP

CHAPTER 2System Bus InterfaceSYS'TE MDA :rABUS,16 ~32 ~J16,,161,4t!: g; a:~~~~ "ffi t-~ :;:$1--r-c-ir'- g;ffi1;: III:;:) gltIIIENABLE IBY PIKELtT ENABLE IBY P -ANEIDIREC:r1ON(Polarity dependent onbuffer type used)'" ;!; OPDMC 0'" 6CQPDM1ACKD--~~(FROMDMA)WRBUS-AS-r---~ PALAl 16A4B~ r--EDEr-r-CSPIXEL ------CSPLANE"'--Figure 2.3-9 Transceiver Configuration to System Bus (2-QPDM System)Note: The DSACK logic would need to respond to anaccess to these addresses, otherwise the system buswould lock up with infinite WAIT states inserted.Bidirectional Buffer Direction ControlThe direction control of the buffers is a simple decode ofthe system write (WRBUS) line and the acknowledge(ACKD) line from the DMA channel associated with theData FIFOs. The ACKD line is required to indicate thatthe sense of the WRBUS line is inverted when transferringdata between the system bus and the Data FIFOs in"fly-by" mode. An example of the PAL code to achievethis function for a 2 QPDM system is shown inAppendix 2.2_3.11 Interrupt HandlingThere are a number of conditions that cause theAm95C60 to raise interrupts to the host processor toinform it of some specific event or an illegal condition.The different types of interrupts that the Am95C60 cangenerate are listed in Figure 2.3-10 All interrupts arernaskable.The interrupt signal from the Am95C60 typically will beconnected to some priority encode scheme, so that allthe sources of interrupt within the system can be arrangedby priority. (See Figure 2.3-11)- Idle- Stack Overflow- Display Memory Boundary Crossed- Clipping Boundary Crossed- Frame- FREQ (Instruction FIFO DMA Control)- DREQ (Data FIFO DMA Control)-- Vertical Blank- Software (The SIGNAL Instruction)" orPicking Detect (Non-maskable)""Note: "Software" and "Picking Detect" conditions set the same interrupt bit in the interruptregister. However, ·Picking Detect" is only enabled when picking is enabled.Figure 2.3-10 Am95C60 Interrupt Sources2-43