Advanced Micro Devices - FTP

CHAPTER 5Evaluation and Demonstration Board5.2.2 Write Enable BufferThe four write enables from the QPDM are buffered inhalf of an Am2966 (reference designator U5 shown onSheet 5 of the schematic diagram). Each output drivesfour VRAMs with a maximum of 5 pF input capacitanceeach, for a total of 20 pF. Using the chart in the 2966 datasheet, we estimate the delay through this buffer to bebetween 6 and 11 ns.5.2.3 XFG BufferXF/G from the QPDM drives four inputs of an Am2966(reference designator U2 shown on Sheet 5 of theschematic diagram). Each of the four outputs of thisdevice drives four VRAM inputs. Each VRAM input has5 pF input capacitance so that each 2966 is driving 20 pF.From the chart in the 2966 data sheet, we estimate thedelay throug,h this buffer will be between 6 and 11 ns.5.2.4 RAS BufferRAS from the QPDM drives four inputs of an Am2966(reference designator U2 shown on Sheet 5 of theschematic diagram). Each of the four outputs of thisdevice drives four VRAM inputs. Each VRAM input has7 pF input capacitance so that each 2966 output is driving28 pF. From the chart in the 2966 data sheet, we estimatethe delay through this buffer to be between 7 and 12 ns.Since the XFG and RAS buffers reside on the same chip,we expect the delays to track. That is, if the XFG buffersare especially slow (due to temperature, VCC, or processing)we expect that the RAS buffers to be also slow.5.2.5 CAS PAL DeviceThe equations forthe PAL device that generates CAS aregiven in Section 5.9.4. This is an Am18P8B, referencedesignator U3. This device is shown on Sheet 8 of theschematic diagram.ASignalcalied !XFER is generated for use inside the PALdevice. This term is active during any transfer cycle fromthe time XF/G falls until RAS rises. The first min-termdetects that XF/G has fallen before RAS (which happensonly at the beginning of a transfer cycle) and the secondmin-term serves to latch the signal until RAS rises at theend of the cycle.Four separate but identical ICAS terms are generated,one for each four VRAMs. This duplication keeps loadingbelow 50 pF so that the PAL device timing parametersare guaranteed. This also minimizes the length of tracenecessary to help reduce undershoot.There are three min-terms in the CAS equations. Thefirst makes CASn whenever CAS is active and XF/G isnot. This occurs during write and refresh cycles. Thesecond min-term makes CASnwhenever Delayed XF/G(DXFG) is active and XFER is inactive. This occurs onlyduring read cycles. The purpose is to generate CAS asearly as possible during read cycles. We delay XF/G justlong enough to guarantee that the Column Address SetupTime will be met. The third min-term for CASn iswhenever CAS is active and XFER is active, This is thecase during a transfer cycle.Delayed Transfer (DL YFER*) is used to force the extraclock pulse required by the VRAMs before serializationbegins. This is generated at the very end of the transfercycle by passing XFER back through the PAL device.Two additional terms that have absolutely nothing to dowith the display memory interface are generated in thisdevice. Active LOW RESET* is generated by invertingRESET from the backplane. A high-frequency filter hasbeen added to this outputto minimize noise on the QPDMReset line. Synchronized Composite Sync (SCS) isgenerated by combining Synchronized Vertical Sync(SVS) with Synchronized Horizontal Sync (SHS). This isdone with an exclusive-OR function.5.3 TIMING GENERATORThe timing generator emphasizes simplicity and clearnessof thought. Using standard (40 ns) PAL devices, itsupports a dot clock of up to 25 MHz. Using -A (25 ns)PAL devices, it will operate at up to 40 MHz.5.3.1 The Oscillator and BuffersThe Dot Clock oscillator is a standard TTL crystal oscillator,reference designator Y1. In the standard QPDMboard configured for the NEC MultiSync (tm) or equivalent,this is a 24 MHz oscillator. It is buffered in four piecesof 74S244 (reference designator U4) making the termsDCLKO-DCLK3. The purpose of the careful clock distributionis to avoid the problems that result from not beingcareful about clock distribution. The oscillator and bufferare shown on Sheet 8 of the schematic diagram.5.3.2 The COUNT PAL DevicesThis AM 16R8 is used to generate the basic timing for theserializers, reference designator U1 O. The equations forthis PAL device are shown in Section 5.9.5. The deviceis shown on Sheet 2 of the schematic diagram.5-4