Advanced Micro Devices - FTP

CHAPTER 2System Bus InterfaceAppendix 3 shows an example of the Source Code forsuch a PAL device.For all devices that use the Autovector facility, no individuallACKline need be set to that device, only the AVECline asserted to the MC68020. As described above, thedevice detects that the interrupt is being serviced (interruptacknowledged) when the Interrupt AcknowledgeRegister is written. which will clear the relevant interruptbits that, when set, cause the interrupt line to be asserted.Interrupt Handling within a Multi-Am95C60 SystemAs all Am95C60s within a system execute the sameinstruction in synchronism, any interrupt conditions detectedby one Am95C60 will also be detected by all otherAm95C60s.By reading the Status Register of any Am95C60, anyoutstanding interrupt condition across all Am95C60s canbe detected. To clear such an interrupt condition acrossall Am95C60s, a Write to the Interrupt AcknowledgeRegister of all Am95C60s can be achieved simultaneously,thus ca\Jsing the desired interrupt condition to beacknowledged and cleared.Using the Arbitration and Bus Cycle Response schemesimplemented by the MC68020, it is simple to interfacetwo devices on the same bus, each running asynchronouslyfrom their own clock source.To gain the most performance from the MC68020, thedevice should be operated at the highest clock ratedefined within the specification of the part (currently16.67 MHz). However, the Ann95C60 is capable ofrunning on a 20 MHz clock for maximum performance indrawing and data transfer operations. If maximumperformance is desired from each device, then each willrun from asynchronous clock sources.Since the definition of the Bus Cycle for accesses to theAm95C60 does not define a relationship to the Am95C60clock, the CSQPDM(N), WRQPDM and RDQPDM signalsmay be asserted in synchronism with the MC68020clock. Any asynchronicity will be handled by theAm95C60 provided that the maximum and minimumspecified figures are complied with. Conversely, inresponding to the bus cycle, it is feasible to generate theDSACK response signals from the Am95C60 clock, asthe MC68020 has internal logic to resynchronize thesesignals to the MC68020 clock. Depending on whetherthe response is synchronous or asynchronous, differenttimings are given in the MC68020 timing definitions,defining the specification of the DSACK responsesignals.DSACK Response GenerationDependent upon other system constraints, it will probablybe more simple to generate the DSACK responsessynchronously to the MC68020 clock using a fixed delaylogic sequence to define the length of any access to theAm95C60. On detecting an access to an Am95C60,sampling using the MC68020 clock, a timing sequencecan be initiated that at some programmed delay afterdetecting the access can generate a synchronousDSACK response. An example of how this may beimplemented is shown in Figure 2.3-12.Example of How DSACK Response May beGeneratedUsing a PAL device with pull-up resistors on each registeredoutput, the registers can be clocked with theASWRBUSCSOPDMCSPiXELCSPl.ANECLK60 nsREGEN 11PAL16R4BUnused=:; ~} State CounterCOUNT 2DSACK 1RDOPDMWROPDMQPDMENNOTE 1: 1 k Ohm pull-up resistors are required on the registerthree-state outputs.NOTE 2: The CSQPDM signal must be synchronous to the clock.Figure 2.3-12 DSACK Response Generation using a PAL2-46