Advanced Micro Devices - FTP

CHAPTER 1Overviewservice. As with the FREQ bit, this condition can be testedby polling, by letting it generate an interrupt, or by theAND structure of the open-drain DREQ node.In addition, a dedicated DMA channel can service theBlock FIFO butTer. The Acknowledge Data, ACKD, lineallows the DMA channel to accommodate a two-bus-cycleDMA transfer (Flow-Thru Mode) or a single-bus-cycletransfer (Fly-By Mode).When transferring data between system bus and displaymemory, the user can access the data by plane orpixel. A by-plane access transfers 16 bits from one plane.On the other hand, a by-pixel access transfers a completepixel, meaning one-bit from each plane.For best efficiency, a designer should choose a transferscheme that fills the 68020's 32-bit-wide data word. Forexample, in a two-graphics processor system, a by-planeaccess transfers 16 bits from each of two planes to the 32-bit bus. Or a by-pixel access allows four 8-bit deep pixelsto be transferred to the CPU's bus.The example application of a two-graphics processorsystem needs additional data butTers between the systembus and the graphic processors' data lines. These butTersmultiplex the relevant data lines to the correct data bitson the bus (Fig. 3).The 68020 uses the Chip Select lines to enable the butTersand chooses between the additional or the standardaccess butTers. The choice is implemented by the CPU'saddress bits As and A., which enable the relevant databus driver. They select either a l6-bit-wide broadcast accessusing bits 16 through 31, a 32-bit by-plane access oftwo planes, or a 32-bit by-pixel access offour 8-bit pixels.Addressing the Am95C60'sinternal resources68020 address linesfunction desired A. A, A, A, A, A,Access instruction FIFO register forwrite access and access statusregister for read access X X X X a aAccess block In/out FIFO register X X X X a 1Access I/O pointer X X X X 1 aAccess register pointed to byIjOpointer X X X X 1 1Both Quod Pixel Data Managersore accessed (broadcast) X X a a X XDevice 1 is accessed X X a 1 X XDevice 2 is accessed X X 1 a X XReserved X X 1 1 X X16-bit wide broadcast a a X X X XDouble 16-bit data transfer a 1 X X X XFour pixel with 8 bits each 1 a X X X XReserved 1 1 X X X XAJ through At, ore undefinableTen maskable conditions in the Am95C60 can signalinterrupts to the CPU over the INT output. Typically,this signal connects to a priority encoder that arrangesthe interrupts for servicing in preferred order. The encoderthen asserts the relevant interrupt levels on the CPU'sInterrupt Level Priority lines, ILP" to ILP ,.When the CPU detects an interrupt level greater thanthe current one, it waits until the end of the current instruction,saves its state, and generates an interrupt acknowledgebus cycle to find out which device has raisedthe interrupt. The device responds with either a vectornumber or by asserting AVEC, which requests an internallygenerated vector. The Am95C60 employs the autovectormethod to handle interrupt acknowledge. Bothmethods point to an interrupt service routine.On entering the interrupt service routine, the CPUsoftware reads the graphics processor's status register tofind out which interrupts are outstanding. The CPUclears the bits for the interrupt it will service by writing tothe graphics controller's interrupt acknowledge registerand then it re-enables its interrupt system. Writing theregister not only tells the graphics chip that the CPU hasserviced the interrupt, but it also clears the relevant interruptbits, which, when set, assert the interrupt line.Because all Am95C60 controllers in a multi-unit systemexecute the same instruction simultaneously, any interruptwill be detected by all the devices, and flagged intheir status registers. The 68020 reads the status registerof one quad pixel data-flow manager, using its individualChip Select address, to avoid having several chips drivethe data bus at the same time. A Write signal to the interruptacknowledge register of all the Am95C60s clears theinterrupt on all the chips. 0Stuart Tindall is a field applications engineer specializingin graphics products. He works out of AMD's UK office inWarrington. Tindall received his electronic engineeringdegree from Liverpool University, UK.Achim Strupat, a field application engineer in AMD'sSouthern Calzfornia office, previously was a member of theQuad Pixel Dataf/ow Manager product- planning group inSunnyvale, Calif Strupat earned his MSEE at the RheinischWestfaelisch Technische Hochscule in Aachen, WestGermany.1-5