Introduction to Microcontrollers Lab Manual - Microchip

2.1 INTERRUPTS
2.2 PRE-LAB
2.1.1 Objective
Lab 2. Interrupts
LABS
This lab covers the following concepts:
• Using interrupts on the PIC24F
• Using the MPLAB IDE Watch window to inspect real-time register values during
programming debugging
2.2.1 Reference Material
• PIC24FJ256GB110 Family Data Sheet (DS39897)
• 16-Bit MCU and DSC Programmer’s Reference Manual (DS70157)
• MPLAB IDE User’s Guide (DS51519)
• PIC24F Family Reference Manual – Section 8. Interrupts (DS39707)
• PIC24F Family Reference Manual – Section 14. Timers (DS39704)
2.2.2 Interrupts
An interrupt (also called an exception) is an asynchronous signal or a synchronous
software event intended to inform the processor that there is a need for a change in
execution.
Interrupts were introduced to avoid wasting the processor’s time in a polling loop. This
method means the processor is fully executing while waiting for an external event, often
without the ability to handle other system events.
When an interrupt occurs, it causes the processor to save its current state on the software
stack and then execute a special subroutine. The Interrupt Vector Table is a list
of the addresses to these special routines. The PIC24F allows for the possibility of a
unique subroutine for each interrupt source.
The special subroutines are known as Interrupt Service Routines (ISRs). It is good
design practice for an ISR to execute as quickly as possible, so the processor should
spend as little time in the ISR as possible. This becomes an issue when you have multiple,
real-time, nested interrupts. In all cases, loops and polling should be avoided in
any ISR.
The main difference between an ISR and a normal subroutine is that before executing
an ISR, the processor saves its current state so that when the ISR is complete, the processor
state can be exactly reproduced and program flow will continue as if the interrupt
did not occur (with the exception of any changes caused by the ISR itself). As a
result, the last instruction of an ISR must be a RETFIE instruction. This restores the
processor state.
2011 Microchip Technology Inc. DS51963A-page 19