Introduction to Microcontrollers Lab Manual - Microchip

8.2.7 Serial Peripheral Interface (SPI)
SPI was created by Motorola. The SPI bus, also referred to as the “four wire” bus, is a
single master multiple slave full duplex synchronous serial interface. The SPI operates
with a single master and one or more slave devices. Only one device can talk to the
master at any given time. Therefore, a chip select or “Slave Select (SS)” is required
from the master to each slave device. When more the one slave device is connected
to the SPI bus, these slave devices are required to tri-state their MISO output when
they are not selected. Devices without tri-state outputs cannot share an SPI bus and
therefore can only be used in a single slave configuration.
The master pulls the Slave Select Low for the desired Slave device and sends a bit on
the MOSI line. The master must then wait if the slave device requires a wait period,
which is often the case for Analog-to-Digital Converters.
Next, the master issues clock cycles. A full duplex transmission occurs during each
clock cycle. The master drives the clock line high. On the rising edge of the clock, the
slave reads in the bit on the MOSI line and shifts out the MSB from its shift register onto
the MISO line. The master drives the clock low and reads the MISO line and places its
next bit on the MOSI line. The master drives the clock high and the clock cycle repeats.
Note: The master must clock in an extra eight dummy bits to read the last eight bits
from the slave.
FIGURE 8-1: SIMPLIFIED SPI SYSTEM
FIGURE 8-2: GENERIC SPI TIMING
2011 Microchip Technology Inc. DS51963A-page 59