Introduction to Microcontrollers Lab Manual - Microchip

FIGURE 7-3: OUTPUT COMPARE BLOCK DIAGRAM
The OCx outputs must be assigned to an available RPn pin before use.
7.2.4 PWM Duty Cycle
The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The
OCxRS and OcxR registers can be written to at any time, but the duty cycle value is
not latched until the period is complete. This provides a double buffer for the PWM duty
cycle and is essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty cycle include:
• If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low
(0% duty cycle).
• If OCxRS is greater than PRy, the pin will remain high (100% duty cycle).
7.2.5 Edge-Aligned PWM Mode Operation
When synchronization occurs, the following five events occur on the next increment
cycle:
• The timer is reset to zero and resumes counting
• The OCx pin is set high (exception: if OCxRS = 0000, the OCx pin would not be
set)
• The OCxR and OCxRS Buffered registers are updated from OCxR and OCxRS
• Interrupt flag, OCxIF, is set
• When the timer and OCxR match, the pin would be set low. This match does not
generate interrupts.
Figure 7-4 depicts the output compare pin over time with OCxR = 0x0000 and OCxRS
= 0x5000.
2011 Microchip Technology Inc. DS51963A-page 53