LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
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Logic Design Laboratory Manual 23<br />
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ii) DE-MUX USING NAND GATES<br />
Enable<br />
Inputs<br />
Data<br />
Input<br />
Select<br />
Inputs<br />
Outputs<br />
E D S 1 S 0 Y 3 Y 2 Y 1 Y 0<br />
1 0 X X X X X X<br />
0 1 0 0 0 0 0 1<br />
0 1 0 1 0 0 1 0<br />
0 1 1 0 0 1 0 0<br />
0 1 1 1 1 0 0 0<br />
VERIFICATION OF IC 74139 (DEMUX)<br />
TRUTH TABLE<br />
Inputs<br />
Outputs<br />
Ea S 1 S 0 Y 3 Y 2 Y 1 Y 0<br />
1 X X 1 1 1 1<br />
0 0 0 1 1 1 0<br />
0 0 1 1 1 0 1<br />
0 1 0 1 0 1 1<br />
0 1 1 0 1 1 1
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