LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
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Logic Design Laboratory Manual 42<br />
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5. CONVERSION OF SR-FLIP FLOP TO JK-FLIP FLOP<br />
<strong>LOGIC</strong> DIAGRAM<br />
TRUTH TABLE<br />
Clock J K Q+ Q’+ Comment<br />
1 0 0 Q Q’<br />
No<br />
Change<br />
1 0 1 0 1 Reset<br />
1 1 0 1 0 Set<br />
1 1 1 Q’ Q Toggle<br />
<strong>LOGIC</strong> DIAGRAM<br />
TRUTH TABLE<br />
SD RD Clock J K Q Q’ Comment<br />
0 0 Not Allowed<br />
0 1 X X X 1 0 Set<br />
1 0 X X X 0 1 Reset<br />
1 1 1 0 0 NC NC Memory<br />
1 1 1 0 1 0 1 Reset<br />
1 1 1 1 0 1 0 Set<br />
1 1 1 1 1 Q’ Q Toggle<br />
6. JK MASTER SLAVE FLIP FLOP<br />
<strong>LOGIC</strong> DIAGRAM