LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
LOGIC DESIGN LABORATORY MANUAL - VTU e-Learning Centre
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Logic Design Laboratory Manual 7<br />
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I. TO REALIZE HALF ADDER<br />
TRUTH TABLE<br />
INPUTS OUTPUTS<br />
A B S C<br />
BOOLEAN EXPRESSIONS:<br />
S=A ⊕ B<br />
C=A B<br />
0 0 0 0<br />
0 1 1 0<br />
1 0 1 0<br />
1 1 0 1<br />
i) Basic Gates ii) NAND Gates<br />
II.<br />
FULL ADDER<br />
TRUTH TABLE<br />
INPUTS OUTPUTS<br />
A B Cin S C<br />
0 0 0 0 0<br />
0 0 1 1 0<br />
0 1 0 1 0<br />
0 1 1 0 1<br />
1 0 0 1 0<br />
1 0 1 0 1<br />
1 1 0 0 1<br />
1 1 1 1 1<br />
BOOLEAN EXPRESSIONS:<br />
S= A ⊕ B ⊕ C<br />
C=A B + B Cin + A Cin<br />
i)BASIC GATES
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