Burn-in & Test Socket Workshop - BiTS Workshop

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BIB Over-current Protective Device (1) • Fuses are commonly used to isolate and protect the UUT on BIB. • Using correct fuse current rating, type (fast or slow-acting) and derating factor is important to avoid circuit electrical over-stress. Fuse rating = Normal Operating Current/0.75 x % rating Burnt Trace Operating Temp vs Fuse Rating % Rating 180 160 140 120 100 80 60 40 20 0 Slow-Acting Fast-Acting PPTC Lack of protection causes die EOS -60C -40C -20C 0C 20C 25C 40C 60C Operating Temp 80C 100C 120C Fuse value is derated with elevated operating temperature • They are current sensitive devices serving as a weak link in BIB circuit. • Fuse characteristic is determined by respond to various current overload. • Slow-acting fuse has more thermal inertia that tolerates initial overload current. • Fast-acting or very fast-acting fuse is good for sensitive, critical circuits. KWLow/Zamel BiTS 2002 7
BIB Over-current Protective Device (.2) • Selection of circuit protective devices depends on - matching circuit characteristic to device specification - operating current, voltage and temperature - required protection device response time - interrupt rating - fault current and - circuit resistance • Burn-in board circuit protection choice. - Wire Fuse low power consumption no leakage current suitable for high voltage & high current circuits one time use only consumable item high maintenance cost Subminiature fuse mounted into turrets Subminiature fuse soldered onto fork connectors Subminiature SMD fuses in receptacles KWLow/Zamel BiTS 2002 8
Page 1 and 2: Burn-in & Test Socket Workshop IEEE
Page 3 and 4: Burn-in & Test Socket Workshop Tech
Page 5 and 6: Agenda • Introduction • UUT Swi
Page 7 and 8: UUT Switching Characteristics(1) Po
Page 9: UUT Switching Characteristics(.3) T
Page 13 and 14: Solutions Investigated • Polymer-
Page 15 and 16: Conclusion • Burn-in board is des
Page 17 and 18: PROTECTING CONDUCTOR PADS ON BURN-I
Page 19 and 20: PROCEDURE • Printed circuit assem
Page 21 and 22: Figure 1. Typical MAP6 board on whi
Page 23 and 24: Contact Resistance For Solder Coate
Page 25 and 26: Resistance Change, Ohms Contact Res
Page 27 and 28: TABLE 1. NUMBER OF OPEN CONTACTS AF
Page 29 and 30: Figure 5. 300 µin thick solder pla
Page 31 and 32: Gold Coating Thickness Requirement
Page 33 and 34: Discussion (continued) • Conducto
Page 35 and 36: CONCLUSIONS • Gold coated conduct
Page 37 and 38: Agenda - Understand BIB Power Decou
Page 39 and 40: Introduction • Existing Time Doma
Page 41 and 42: New PD Optimization(PDO) BKM Start
Page 43 and 44: Ztarget Definition & Relationship W
Page 45 and 46: Cres Effect in Optimization Z (Ω)
Page 47 and 48: PDO - Clocal Optimization Steps Fai
Page 49 and 50: Impedance(mΩ) 4x 3x 2x Example: BI
Page 51 and 52: Conclusion • PDO is a more system

Burn-in & Test Socket Workshop - BiTS Workshop

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