Burn-in & Test Socket Workshop - BiTS Workshop

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Burn-in Board Over-current Circuit Protection - What Are The Options? KW Low/Zamel Jaafar Intel Malaysia 2002 Burn-in and Test Socket Workshop March 3 - 6, 2002
Agenda • Introduction • UUT Switching Characteristics • BIB Over-current Circuit Protective Devices • Manufacturing Issues & Concerns • Solutions Investigated • Technology Challenges • Conclusion • Acknowledgement KWLow/Zamel BiTS 2002 2
Page 1 and 2: Burn-in & Test Socket Workshop IEEE
Page 3: Burn-in & Test Socket Workshop Tech
Page 7 and 8: UUT Switching Characteristics(1) Po
Page 9 and 10: UUT Switching Characteristics(.3) T
Page 11 and 12: BIB Over-current Protective Device
Page 13 and 14: Solutions Investigated • Polymer-
Page 15 and 16: Conclusion • Burn-in board is des
Page 17 and 18: PROTECTING CONDUCTOR PADS ON BURN-I
Page 19 and 20: PROCEDURE • Printed circuit assem
Page 21 and 22: Figure 1. Typical MAP6 board on whi
Page 23 and 24: Contact Resistance For Solder Coate
Page 25 and 26: Resistance Change, Ohms Contact Res
Page 27 and 28: TABLE 1. NUMBER OF OPEN CONTACTS AF
Page 29 and 30: Figure 5. 300 µin thick solder pla
Page 31 and 32: Gold Coating Thickness Requirement
Page 33 and 34: Discussion (continued) • Conducto
Page 35 and 36: CONCLUSIONS • Gold coated conduct
Page 37 and 38: Agenda - Understand BIB Power Decou
Page 39 and 40: Introduction • Existing Time Doma
Page 41 and 42: New PD Optimization(PDO) BKM Start
Page 43 and 44: Ztarget Definition & Relationship W
Page 45 and 46: Cres Effect in Optimization Z (Ω)
Page 47 and 48: PDO - Clocal Optimization Steps Fai
Page 49 and 50: Impedance(mΩ) 4x 3x 2x Example: BI
Page 51 and 52: Conclusion • PDO is a more system

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