Burn-in & Test Socket Workshop - BiTS Workshop
Burn-in & Test Socket Workshop - BiTS Workshop
Burn-in & Test Socket Workshop - BiTS Workshop
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Exist<strong>in</strong>g PD Approach & Drawbacks<br />
Start<br />
Customer Request<br />
Model Setup<br />
Simulation<br />
Vdroop<br />
Documentation<br />
• Non systematic approach<br />
– It’s merely trial-&-error TD<br />
approach decoupl<strong>in</strong>g optimization<br />
• Time consum<strong>in</strong>g<br />
– Many steps taken for optimization<br />
• Unable to understand <strong>in</strong>dividual<br />
capacitor performance/<br />
effectiveness<br />
– Each capacitor is only effective<br />
before its resonant frequency<br />
region<br />
• Thus, it needs a systematic<br />
/effective methodology for a<br />
more comprehensive<br />
optimization solution<br />
02/01/2002 <strong>BiTS</strong> 2002 5<br />
End<br />
Pass<br />
Cap Placement<br />
Check thru design?<br />
Pass<br />
Fail<br />
Optimize<br />
Decoupl<strong>in</strong>g<br />
Fail
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