Lecture Notes for Computer Architecture II - St. Cloud State University

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Lecture 17 Performance Enhancement with added Functionality - Floating Point Adder In Computations We Need Speed Accuracy And range Page | 106 Integers does not provide the accuracy needed in many computations and the range is limited The use of Floating point numbers provide the accuracy and range increase Floating numbers 3.656914 10 2 Sign Digit Fraction Exponent We can use the following format to represent the floating point numbers Sign Exponent Fraction There are two different formats to increase the precision of computations. 64 bit – Double precision 32 bit – Single precision To avoid conflicts between different manufacturers IEEE proposed the standard in 1979 32 bit format Sign Exponent Fraction 1 8 23 64 bit Sign Exponent Fraction 1 11 52
Normalized Form keeps one digit left to the binary point For example 1.000111 This can be written as n (1 + F) 2 Fraction - F Exponent - n Page | 107 In the IEEE standard we have to add 127 to the exponent in single precision In the IEEE standard we have to add 1023 to the exponent in double precision – SP (127) DP (1023) Compromise Accuracy Fraction Range Exponent Example .75 10 .11000 binary .75 X 2 = 1.50 .5 X 2 = 1.0 .75 10 = .11 2 Normalized form 0.11 = 1.1 2 -1 IEEE standard format single precision 0 126 10000000000000 -1 + 127 23 bit Another Example .9 10 .9 * 2 = 1.8 .8 * 2 = 1.6 .6 * 2 = 1.2 .2 *2 = 0.4 .4 * 2 = 0.8 .9 = .11100
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Page | 1 Lecture Notes for Computer
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knowledge given in the book chapter
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CS 320 SCHEDULE (tentative) Week Wh
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6. Project reports - Presentation C
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9. Course policies: 1) Satisfactory
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Size - keep shrinking 1994 124mm 2
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Families of different models - Inte
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Super Computers CRAY - 1 st vector
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Fastest super computers November 20
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Class Activity - 2. Trace the conte
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TUTOR 1.32:> PHYSICAL ADDRESS=00002
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Class Activity 3 - Study of instruc
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Class Activity 4 - Study of instruc
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Performance Improvement at Instruct
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5. Register indirect addressing mod
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High Level Language Statements Ass
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Lecture 7 Data transfer memory reg
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Problem Translate HLL statement A[
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More MIPS instructions jump j jr $S
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Problem Translate the following Whi
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Problem Translate the following exp
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Problem Translate the following exp
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Lecture 10 Translation of High Leve
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Translation of Procedures Problem H
Page 55 and 56: Example Write the MIPS code to comp
Page 57 and 58: Program Counter -relative op rs rt
Page 59 and 60: Example Opcode always 1 byte Memory
Page 61 and 62: Lecture 13 Enhancing Performance at
Page 63 and 64: Number Systems Numbers + ve numbers
Page 65 and 66: Example: Design a one bit ALU with
Page 67 and 68: Lecture 14 - Performance Improvemen
Page 69 and 70: Design of Adders c 1 a n , ..., a 1
Page 71 and 72: Carry lookahead adder Problem with
Page 73 and 74: Another look at CLA xi + yi = Pi xi
Page 75 and 76: 4-bit CLA Page | 75 generates C3 ge
Page 77 and 78: Lecture 15 Performance Improvement
Page 79 and 80: Example 981 X 1234 0981 X 1234 mult
Page 81 and 82: Example Consider the multiplication
Page 83 and 84: 2 nd version Reduce cost by reducin
Page 85 and 86: 4th step 4 bits registers 0010 4 bi
Page 87 and 88: 0010 ADDER Page | 87 0001 0010 ADDE
Page 89 and 90: 2's complement of m'cand 1111110101
Page 91 and 92: 0010 ADDER Page | 91 1111 0001 1 no
Page 93 and 94: Lecture 16 - Performance Improvemen
Page 95 and 96: Hardware units needed to perform th
Page 97 and 98: Step 1 Rem = Rem - Divisor ( this t
Page 99 and 100: 5th step Rem = Rem - Divisor Now Re
Page 101 and 102: 2nd step Shift remainder left Rem =
Page 103 and 104: 3 rd version of Division algorithm
Page 105: Step 3 Rem = Rem - Div Rem > 0 Shif
Page 109 and 110: Let us consider the addition of two
Page 111 and 112: Control path Inputs Exponent differ
Page 113 and 114: Lecture 19 Architectures for Crypto
Page 115 and 116: 1. Following pseudo code represents
Page 117 and 118: Find 7 36 mod 11 using right to lef
Page 119 and 120: Lecture 20 - Performance Chapter -
Page 121 and 122: total amount of work done in a give
Page 123 and 124: Question 4 Assuming the CPI for pro
Page 125 and 126: Question 9 Yet another user has the
Page 127 and 128: Question 12 Assuming the CPI values
Page 129 and 130: Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.
Page 131 and 132: Question 15 We are interested in tw
Page 133 and 134: Question 18 You are the lead design
Page 135 and 136: Arithmetic Logic unit Register file
Page 137 and 138: Lecture 22 - Processor Design - Dat
Page 139 and 140: Example Design the data path to fet
Page 141 and 142: Now combine two functional units to
Page 143 and 144: Lecture 23 Processor Design - Data
Page 145 and 146: Example : - Design DataPath for SW
Page 147 and 148: Processor Design - Data path for R&
Page 149 and 150: Example : - Implement R+ I +J Forma
Page 151 and 152: 31 26 0 4 control signals EX/Addres
Page 153 and 154: Draw the logic circuit _ _ _ _ _ _
Page 155 and 156: Single cycle implementation of the
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from Aluop B from output PC Data Ad
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Lecture 27 High level view of the F
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0 Page | 161 1 2 3 5 4 0 - MemRead
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FSM Controller for lw/sw 6 states 0
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Lecture 28 R-type instruction conti
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Branch Instruction Fetch Page | 167
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Jump Inst Fetch Page | 169 Inst dec
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0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
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NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
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Lecture 30 Microprogramming - FSM c
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- Microinstruction placed in a ROM
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- In multicycle design - assume tha
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Multi-cycle implementation of the M
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2.5 Draw the functional units neces
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2.9 The instruction, addi (add imme
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Problems with pipelining Hazards Da
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Ex: Represent the 5 stage pipeline
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Example Represent the 5 stage pipel
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Example: Find the size of each pipe
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Pipelined control path - Single cyc
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Control signals with instructions E
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Ex: Show the control signals genera
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Ex: Show the control signals genera
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Lecture 33 Forwarding Unit Design E
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Example: Illustrate the forwarding
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Design a Forwarding unit to integra
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Ex: Forwarding with 2 inst. (1) add
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Lecture 34 Data hazard and stalls F
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Tomasulo • Lasting Contributions
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Tomasulo Organization Page | 217
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4. Show the pipeline execution of f
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7. Illustrate the pipelined data pa
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11. Reorder the following instructi
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15. Design the forwarding unit for
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Temporal locality Low Data Accessin
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Associative mapping More flexible m
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Problems 1. Here is a series of add
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6. What are the miss rate of the fo
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Installation and Usage of Maxplus I
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intend to read registers this instr
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Tomasulo hardware algorithm From Wi
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When all operands are available o I
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Lecture Notes for Computer Architecture II - St. Cloud State University

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