Lecture Notes for Computer Architecture II - St. Cloud State University

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Question 13 Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 400GHz, and M2 has a clock rate of 200GHz. The average number of cycles for each instruction class on M1 and M2 is given in the following table: Class CPI on M1 CPI on M2 C1 usage C2 usage Third-party usage A 4 2 30% 30% 50% B 6 4 50% 20% 30% C 8 3 20% 50% 20% Page | 128 The table also contains a summary of how three different compilers use the instruction set. C1 is a compiler produced by the makers of M1, C2 is a compiler produced by the makers of M2, and the other compiler is as third-party product. Assume that each compiler uses the same number of instructions for a given program but that the instruction mix is as described in the table. Using C1 on both M1 and M2, how much faster can the makers of M1 claim that M1 is compared with M2? Using C2 on both M2 and M1, how much faster can the makers of M2 claim that M2 is compared with M2? If you purchase M1, which compiler would you use? If you purchase M2, which compiler would you use? Which machine would you purchase if we assume that all other criteria are identical, including costs? Solution 2 implementations of M1 & M2 of the same instruction set M1 – 400 GHz M2 – 200 GHz - 3 classes of instruction A,B,C - 3 compilers C1,C2,3 rd party - same number of instruction per program Use C1 CPI on M1 = 4*0.3+6*0.5+8*0.2 = 5.8 CPI on M2 = 2*0.3+4*0.5+3*0.2 = 3.2 CPU time = CPI * Inst./Program * Second/Cycles CPU time M1 = 5.8 * 1/400 * x CPU time M2 = 3.2 * 1/200 * x Performance M1 CPU time M2 = Performance M2 CPU time M1 = 1.1
Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.5 = 6.4 CPI on M2 = 2*0.3+4*0.2+3*0.5 = 2.9 Page | 129 CPU time M1 = 6.4/400* x CPU time M2 = 2.9/200* x Performance M1 CPU time M2 = Performance M2 CPU time M1 = 0.90625 Use 3 rd party compiler CPI on M1 = 4*0.5+6*0.3+8*0.2 = 5.4 CPI on M2 = 2*0.5 +4*0.3+3*0.2 = 2.8 CPU time M1 = 5.4/400* x CPU time M2 = 2.9/200* x Performance M1 CPU time M2 = Performance M2 CPU time M1 = 1.04
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Page | 1 Lecture Notes for Computer
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knowledge given in the book chapter
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CS 320 SCHEDULE (tentative) Week Wh
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6. Project reports - Presentation C
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9. Course policies: 1) Satisfactory
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Size - keep shrinking 1994 124mm 2
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Families of different models - Inte
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Super Computers CRAY - 1 st vector
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Fastest super computers November 20
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Class Activity - 2. Trace the conte
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TUTOR 1.32:> PHYSICAL ADDRESS=00002
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Class Activity 3 - Study of instruc
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Class Activity 4 - Study of instruc
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Performance Improvement at Instruct
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5. Register indirect addressing mod
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High Level Language Statements Ass
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Lecture 7 Data transfer memory reg
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Problem Translate HLL statement A[
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More MIPS instructions jump j jr $S
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Problem Translate the following Whi
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Problem Translate the following exp
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Problem Translate the following exp
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Lecture 10 Translation of High Leve
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Translation of Procedures Problem H
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Example Write the MIPS code to comp
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Program Counter -relative op rs rt
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Example Opcode always 1 byte Memory
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Lecture 13 Enhancing Performance at
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Number Systems Numbers + ve numbers
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Example: Design a one bit ALU with
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Lecture 14 - Performance Improvemen
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Design of Adders c 1 a n , ..., a 1
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Carry lookahead adder Problem with
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Another look at CLA xi + yi = Pi xi
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4-bit CLA Page | 75 generates C3 ge
Page 77 and 78: Lecture 15 Performance Improvement
Page 79 and 80: Example 981 X 1234 0981 X 1234 mult
Page 81 and 82: Example Consider the multiplication
Page 83 and 84: 2 nd version Reduce cost by reducin
Page 85 and 86: 4th step 4 bits registers 0010 4 bi
Page 87 and 88: 0010 ADDER Page | 87 0001 0010 ADDE
Page 89 and 90: 2's complement of m'cand 1111110101
Page 91 and 92: 0010 ADDER Page | 91 1111 0001 1 no
Page 93 and 94: Lecture 16 - Performance Improvemen
Page 95 and 96: Hardware units needed to perform th
Page 97 and 98: Step 1 Rem = Rem - Divisor ( this t
Page 99 and 100: 5th step Rem = Rem - Divisor Now Re
Page 101 and 102: 2nd step Shift remainder left Rem =
Page 103 and 104: 3 rd version of Division algorithm
Page 105 and 106: Step 3 Rem = Rem - Div Rem > 0 Shif
Page 107 and 108: Normalized Form keeps one digit lef
Page 109 and 110: Let us consider the addition of two
Page 111 and 112: Control path Inputs Exponent differ
Page 113 and 114: Lecture 19 Architectures for Crypto
Page 115 and 116: 1. Following pseudo code represents
Page 117 and 118: Find 7 36 mod 11 using right to lef
Page 119 and 120: Lecture 20 - Performance Chapter -
Page 121 and 122: total amount of work done in a give
Page 123 and 124: Question 4 Assuming the CPI for pro
Page 125 and 126: Question 9 Yet another user has the
Page 127: Question 12 Assuming the CPI values
Page 131 and 132: Question 15 We are interested in tw
Page 133 and 134: Question 18 You are the lead design
Page 135 and 136: Arithmetic Logic unit Register file
Page 137 and 138: Lecture 22 - Processor Design - Dat
Page 139 and 140: Example Design the data path to fet
Page 141 and 142: Now combine two functional units to
Page 143 and 144: Lecture 23 Processor Design - Data
Page 145 and 146: Example : - Design DataPath for SW
Page 147 and 148: Processor Design - Data path for R&
Page 149 and 150: Example : - Implement R+ I +J Forma
Page 151 and 152: 31 26 0 4 control signals EX/Addres
Page 153 and 154: Draw the logic circuit _ _ _ _ _ _
Page 155 and 156: Single cycle implementation of the
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Page 163 and 164: FSM Controller for lw/sw 6 states 0
Page 165 and 166: Lecture 28 R-type instruction conti
Page 167 and 168: Branch Instruction Fetch Page | 167
Page 169 and 170: Jump Inst Fetch Page | 169 Inst dec
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Page 173 and 174: 0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
Page 175 and 176: NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
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- Microinstruction placed in a ROM
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- In multicycle design - assume tha
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Multi-cycle implementation of the M
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2.5 Draw the functional units neces
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2.9 The instruction, addi (add imme
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Problems with pipelining Hazards Da
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Ex: Represent the 5 stage pipeline
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Example Represent the 5 stage pipel
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Example: Find the size of each pipe
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Pipelined control path - Single cyc
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Control signals with instructions E
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Ex: Show the control signals genera
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Ex: Show the control signals genera
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Lecture 33 Forwarding Unit Design E
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Example: Illustrate the forwarding
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Design a Forwarding unit to integra
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Ex: Forwarding with 2 inst. (1) add
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Lecture 34 Data hazard and stalls F
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Tomasulo • Lasting Contributions
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Tomasulo Organization Page | 217
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4. Show the pipeline execution of f
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7. Illustrate the pipelined data pa
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11. Reorder the following instructi
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15. Design the forwarding unit for
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Temporal locality Low Data Accessin
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Associative mapping More flexible m
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Problems 1. Here is a series of add
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6. What are the miss rate of the fo
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Installation and Usage of Maxplus I
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intend to read registers this instr
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Tomasulo hardware algorithm From Wi
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When all operands are available o I
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