Lecture Notes for Computer Architecture II - St. Cloud State University

7. Illustrate the pipelined data path and control path to improve performance of single
cycle MIPS processor that implements R-type, lw/sw, beq and J instructions. Identify
each pipe line register by the name of the field value that is to be loaded, length of the
field and total length of the pipeline register.
Page | 221
8. Instruction Decode, ID, stage of the pipe line processor receives following instruction
bits:
Bits 15-0 = 2090
20-16 = 11
15-11 = 1
26-21 = 10
Control unit in the ID stage produces 1100 000 10 for EX, MEM and WB stages.
Identify the instruction.