Lecture Notes for Computer Architecture II - St. Cloud State University

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3. Computer Arithmetic Circuits Cost reduction and speed improvement techniques Flip-Flops, Boolean expressions, circuits, literal analysis, symbolic analysis Cryptographic Algorithms and Special Purpose Hardware Reading Assignment – Chapter 3 Homework assignment - Chapter 3 problems 1-10 68K Laboratory Assignments TEST – 2 4. Performance Reading Assignment – Chapter 4 Homework assignment - Chapter 4 problems 1-10 68K Laboratory Assignments TEST – 3 5. Processor Design: Data Path and Control state diagrams, mapping control to hardware, single cycle and multi-cycle implementation Reading Assignment – Chapter 5 Homework assignment - Chapter 5 Problems 1-10 X86 Laboratory Assignments TEST – 4 6. Pipeline Processor Design Enhancing performance, Branch prediction, Speculative execution, Superscalar architecture, Out of Order Execution, Tomasulo Algorithm Reading Assignment – Chapter 6 Homework assignment - Chapter 6 Problems 1-10 X86 Laboratory Assignments TEST – 5 7. Large and Fast Memories Caches, virtual memory, improving performance Reading Assignment – Chapter 7 Homework assignment Chapter 7 Problems 1-10 X86 Laboratory Assignments TEST – 6 8. Storage, Networks and Other peripherals I/O performance, I/O devices, interfacing I/O devices to memory, processor and operating system Reading Assignment – Chapter 8 Homework assignment - Chapter 8 Problems 1-10 9. Multiprocessors Reading Assignment – Chapter 9 Homework assignment - Chapter 9 Problems 1-10 Final Project – Pipelined processor design using VHDL Page | 4 Final Exam TBA
CS 320 SCHEDULE (tentative) Week What Reading 1 Introduction 1 Lecture 1 State-of-the-art 1.1-16 2 Lecture 2 Performance Improvement at Instruction Set level 2.1–2.6 2 Lecture 3 Translation of High Level Language Arithmetic Expressions to MIPS Code 3 Lecture 4 Translation of Data Transfer Expressions to MIPS Code 3 Lecture 5 Translation of If Else, Switch expressions to MIPS Code 3 Lecture 6 Translation of Loop, for, while expressions to MIPS Code 4 Lecture 7 Translation of High Level Language Procedures to MIPS Code 4 Lecture 8 Architectural Styles –Stack Machines, Buffer Overflow 4 Exam 4 Lecture 9 Performance Enhancement by adding Functionality - ALU Design 3.1-3.10 Lecture 10 Performance Enhancement at Gate Level - Adder Circuit Designs 5 Lecture 11 Performance Enhancement at Register level - Multiplier Circuit Designs 5 Lecture 12 Performance Enhancement at Register level - Divider Circuit Designs 5 Lecture 13 Performance Enhancement at Register level - Floating point Adder Design 6 Lecture 14 Algorithmic Transformation for Designing Cryptographic Hardware 6 Exam 7 Lecture 15 Performance 4.1-4.8 8 Performance 8 Exam 8 Lecture 16 Performance Enhancement at Processor level - Arithmetic, Branch, Jump 5.1-5.8 9 Lecture 17 Controller Design 9 Lecture 18 Performance Enhancement at Processor level - Multi Cycle implementation 10 Lecture 19 Design of Controllers for Multi Cycle Processor Finite State Machine 10 Lecture 20 Design of Controllers for Multi Cycle Processor - Microprogramming 11 Lecture 21 Transformation from Finite State Machine to Micro Program 11 Exam 11 Lecture 22 Performance Enhancement of Processor Design - Pipelining 6.1-6.10 12 Lecture 23 Performance Enhancement - Data hazards, stalls and forwarding 12 Lecture 24 Performance Enhancement - Branch hazards, Exceptions 12 Lecture 25 Performance Enhancement - Loop unfolding, Superscalar and dynamic pipelining 13 Exam 13 Lecture 26 Performance Enhancement - Memory Hierarchy 7.1-7.5 13 Lecture 27 Performance Enhancement - Cache, Virtual memory 14 Lecture 29 I/O 14 Lecture 30 Performance Enhancement – Multi - Processors 9.1-9.7 15 Lecture 31 Multi - Processors 15 Final Exam Page | 5
Page 1 and 2: Page | 1 Lecture Notes for Computer
Page 3: knowledge given in the book chapter
Page 7 and 8: 6. Project reports - Presentation C
Page 9 and 10: 9. Course policies: 1) Satisfactory
Page 11 and 12: Size - keep shrinking 1994 124mm 2
Page 13 and 14: Families of different models - Inte
Page 15 and 16: Super Computers CRAY - 1 st vector
Page 17 and 18: Fastest super computers November 20
Page 19 and 20: Class Activity - 2. Trace the conte
Page 21 and 22: TUTOR 1.32:> PHYSICAL ADDRESS=00002
Page 25 and 26: Class Activity 3 - Study of instruc
Page 27 and 28: Class Activity 4 - Study of instruc
Page 33 and 34: Performance Improvement at Instruct
Page 35 and 36: 5. Register indirect addressing mod
Page 37 and 38: High Level Language Statements Ass
Page 39 and 40: Lecture 7 Data transfer memory reg
Page 41 and 42: Problem Translate HLL statement A[
Page 43 and 44: More MIPS instructions jump j jr $S
Page 45 and 46: Problem Translate the following Whi
Page 47 and 48: Problem Translate the following exp
Page 49 and 50: Problem Translate the following exp
Page 51 and 52: Lecture 10 Translation of High Leve
Page 53 and 54: Translation of Procedures Problem H
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Example Write the MIPS code to comp
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Program Counter -relative op rs rt
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Example Opcode always 1 byte Memory
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Lecture 13 Enhancing Performance at
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Number Systems Numbers + ve numbers
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Example: Design a one bit ALU with
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Lecture 14 - Performance Improvemen
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Design of Adders c 1 a n , ..., a 1
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Carry lookahead adder Problem with
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Another look at CLA xi + yi = Pi xi
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4-bit CLA Page | 75 generates C3 ge
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Lecture 15 Performance Improvement
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Example 981 X 1234 0981 X 1234 mult
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Example Consider the multiplication
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2 nd version Reduce cost by reducin
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4th step 4 bits registers 0010 4 bi
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0010 ADDER Page | 87 0001 0010 ADDE
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2's complement of m'cand 1111110101
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0010 ADDER Page | 91 1111 0001 1 no
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Lecture 16 - Performance Improvemen
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Hardware units needed to perform th
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Step 1 Rem = Rem - Divisor ( this t
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5th step Rem = Rem - Divisor Now Re
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2nd step Shift remainder left Rem =
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3 rd version of Division algorithm
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Step 3 Rem = Rem - Div Rem > 0 Shif
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Normalized Form keeps one digit lef
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Let us consider the addition of two
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Control path Inputs Exponent differ
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Lecture 19 Architectures for Crypto
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1. Following pseudo code represents
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Find 7 36 mod 11 using right to lef
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Lecture 20 - Performance Chapter -
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total amount of work done in a give
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Question 4 Assuming the CPI for pro
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Question 9 Yet another user has the
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Question 12 Assuming the CPI values
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Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.
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Question 15 We are interested in tw
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Question 18 You are the lead design
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Arithmetic Logic unit Register file
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Lecture 22 - Processor Design - Dat
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Example Design the data path to fet
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Now combine two functional units to
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Lecture 23 Processor Design - Data
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Example : - Design DataPath for SW
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Processor Design - Data path for R&
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Example : - Implement R+ I +J Forma
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31 26 0 4 control signals EX/Addres
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Draw the logic circuit _ _ _ _ _ _
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Single cycle implementation of the
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from Aluop B from output PC Data Ad
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Lecture 27 High level view of the F
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0 Page | 161 1 2 3 5 4 0 - MemRead
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FSM Controller for lw/sw 6 states 0
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Lecture 28 R-type instruction conti
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Branch Instruction Fetch Page | 167
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Jump Inst Fetch Page | 169 Inst dec
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Page | 171
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0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
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NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
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Lecture 30 Microprogramming - FSM c
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- Microinstruction placed in a ROM
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- In multicycle design - assume tha
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Multi-cycle implementation of the M
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2.5 Draw the functional units neces
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2.9 The instruction, addi (add imme
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Problems with pipelining Hazards Da
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Ex: Represent the 5 stage pipeline
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Example Represent the 5 stage pipel
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Example: Find the size of each pipe
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Pipelined control path - Single cyc
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Control signals with instructions E
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Ex: Show the control signals genera
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Ex: Show the control signals genera
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Lecture 33 Forwarding Unit Design E
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Example: Illustrate the forwarding
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Design a Forwarding unit to integra
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Ex: Forwarding with 2 inst. (1) add
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Lecture 34 Data hazard and stalls F
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Tomasulo • Lasting Contributions
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Tomasulo Organization Page | 217
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4. Show the pipeline execution of f
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7. Illustrate the pipelined data pa
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11. Reorder the following instructi
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15. Design the forwarding unit for
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Temporal locality Low Data Accessin
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Associative mapping More flexible m
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Problems 1. Here is a series of add
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6. What are the miss rate of the fo
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Installation and Usage of Maxplus I
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intend to read registers this instr
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Tomasulo hardware algorithm From Wi
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When all operands are available o I
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Lecture Notes for Computer Architecture II - St. Cloud State University

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