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Lecture Notes for Computer Architecture II - St. Cloud State University

Lecture Notes for Computer Architecture II - St. Cloud State University

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intend to read registers this instruction wants to write to—have completed their<br />

read operands stage. This way, so called data dependencies (WAR - Write after<br />

Read) can be addressed.<br />

Data structure<br />

Page | 237<br />

To control the execution of the instructions, the scoreboard maintains three status<br />

tables:<br />

Instruction <strong>St</strong>atus: Indicates, <strong>for</strong> each instruction being executed, which of<br />

the four stages it is in.<br />

Functional Unit <strong>St</strong>atus: Indicates the state of each functional unit. Each<br />

function unit maintains 9 fields in the table:<br />

Busy: Indicates whether the unit is being used or not<br />

Op: Operation to per<strong>for</strong>m in the unit (e.g. MUL, DIV or MOD)<br />

F i : Destination register<br />

F j ,F k : Source-register numbers<br />

Q j ,Q k : Functional units that will produce the source registers F j , F k<br />

R j ,R k : Flags that indicates when F j , F k are ready<br />

Register <strong>St</strong>atus: Indicates, <strong>for</strong> each register, which function unit will write<br />

results into it.

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