Lecture Notes for Computer Architecture II - St. Cloud State University

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Game Processors SS - 1994 – 1 million trs DC- 1997 – 5 million trs Graphics Synthesizer 75 million polygons/sec 279mm 2 10W @ 1.8V 384 pins 5 metal layers Peak Performance Pentium II - Pentium III- Pentium IV 400MHz 1.5 GIPS 0.5 GFlops 600 MHz 2 GIPS 2.5 Gflops Polygon rendering performance 94 PC 500,000 polygon/sec GNS 1 million polygon/sec 96 N64 - 3 million polygon/sec GNS – 7 million polygon/sec PC – 500,000 polygon/sec 97 PC – 700,000 polygon/sec GNS – 10 million polygon/sec 98 GNS – 20 million polygon/sec PCS – 4 million polygon/sec 99 PC – 7 million polygon/sec GNS – 30 million polygon/sec PS2 – 100 million polygon/sec 2005 Nividia 165 GFlops Performance increase five fold every 18 months 3GHZ Pentium-4s arithmetic unit runs at 24Gflops Attributes of a system - Visible to the programmer (Assembly Languages) Instruction set Number of bits used for various data types Techniques for addressing memory I/O mechanisms Page | 12
Families of different models - Intel X86 - Motorola MC68000 - IBM CPU - ALU(Arithmetic Logic Unit) - Control Unit - Register - Interconnection Rapidly changing circuit design VLSI (Hundreds of thousand transistors) 2.5 million times IC (100’s of transistors) 900 Tr 35 Vacuum Tubes 1 Processor speed doubled every 1.5 years History Year Model Size Speed Memory Price Power 1951 Univac 1000fts 3 1900add/sec 48KB 1 million 124,000watts 1964 IBM360 60fts 3 500.000add/sec 64KB 10.000watts Iowa State U Atkinson 40’s – 1 st special purpose Mauchly visited U of Penn. Built ENIAC 1945 – Mauchly Von Neumann visited U of Penn. And wrote paper ENIAC – U of Penn. - Mauchly - General purpose computer - 80 feet long - 8.5 feet high - 3.4 feet wide - vacuum tube 18,000 Germany Zuse 1930s – special purpose IBM 30 family – 1964 40 - 1.6MHz 32KB – 256KB memory $225,000 50 – 2.0MHz 12KB – 256KB memory $550,000 65 – 5MHz 256KB – IMB memory $1,200,000 75 – 5.1MHz 256KB – 1MB memory $1,900,000 Page | 13
Page 1 and 2: Page | 1 Lecture Notes for Computer
Page 3 and 4: knowledge given in the book chapter
Page 5 and 6: CS 320 SCHEDULE (tentative) Week Wh
Page 7 and 8: 6. Project reports - Presentation C
Page 9 and 10: 9. Course policies: 1) Satisfactory
Page 11: Size - keep shrinking 1994 124mm 2
Page 15 and 16: Super Computers CRAY - 1 st vector
Page 17 and 18: Fastest super computers November 20
Page 19 and 20: Class Activity - 2. Trace the conte
Page 21 and 22: TUTOR 1.32:> PHYSICAL ADDRESS=00002
Page 25 and 26: Class Activity 3 - Study of instruc
Page 27 and 28: Class Activity 4 - Study of instruc
Page 33 and 34: Performance Improvement at Instruct
Page 35 and 36: 5. Register indirect addressing mod
Page 37 and 38: High Level Language Statements Ass
Page 39 and 40: Lecture 7 Data transfer memory reg
Page 41 and 42: Problem Translate HLL statement A[
Page 43 and 44: More MIPS instructions jump j jr $S
Page 45 and 46: Problem Translate the following Whi
Page 47 and 48: Problem Translate the following exp
Page 49 and 50: Problem Translate the following exp
Page 51 and 52: Lecture 10 Translation of High Leve
Page 53 and 54: Translation of Procedures Problem H
Page 55 and 56: Example Write the MIPS code to comp
Page 57 and 58: Program Counter -relative op rs rt
Page 59 and 60: Example Opcode always 1 byte Memory
Page 61 and 62: Lecture 13 Enhancing Performance at
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Number Systems Numbers + ve numbers
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Example: Design a one bit ALU with
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Lecture 14 - Performance Improvemen
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Design of Adders c 1 a n , ..., a 1
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Carry lookahead adder Problem with
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Another look at CLA xi + yi = Pi xi
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4-bit CLA Page | 75 generates C3 ge
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Lecture 15 Performance Improvement
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Example 981 X 1234 0981 X 1234 mult
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Example Consider the multiplication
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2 nd version Reduce cost by reducin
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4th step 4 bits registers 0010 4 bi
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0010 ADDER Page | 87 0001 0010 ADDE
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2's complement of m'cand 1111110101
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0010 ADDER Page | 91 1111 0001 1 no
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Lecture 16 - Performance Improvemen
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Hardware units needed to perform th
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Step 1 Rem = Rem - Divisor ( this t
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5th step Rem = Rem - Divisor Now Re
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2nd step Shift remainder left Rem =
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3 rd version of Division algorithm
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Step 3 Rem = Rem - Div Rem > 0 Shif
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Normalized Form keeps one digit lef
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Let us consider the addition of two
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Control path Inputs Exponent differ
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Lecture 19 Architectures for Crypto
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1. Following pseudo code represents
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Find 7 36 mod 11 using right to lef
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Lecture 20 - Performance Chapter -
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total amount of work done in a give
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Question 4 Assuming the CPI for pro
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Question 9 Yet another user has the
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Question 12 Assuming the CPI values
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Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.
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Question 15 We are interested in tw
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Question 18 You are the lead design
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Arithmetic Logic unit Register file
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Lecture 22 - Processor Design - Dat
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Example Design the data path to fet
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Now combine two functional units to
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Lecture 23 Processor Design - Data
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Example : - Design DataPath for SW
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Processor Design - Data path for R&
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Example : - Implement R+ I +J Forma
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31 26 0 4 control signals EX/Addres
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Draw the logic circuit _ _ _ _ _ _
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Single cycle implementation of the
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from Aluop B from output PC Data Ad
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Lecture 27 High level view of the F
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0 Page | 161 1 2 3 5 4 0 - MemRead
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FSM Controller for lw/sw 6 states 0
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Lecture 28 R-type instruction conti
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Branch Instruction Fetch Page | 167
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Jump Inst Fetch Page | 169 Inst dec
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Page | 171
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0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
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NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
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Lecture 30 Microprogramming - FSM c
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- Microinstruction placed in a ROM
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- In multicycle design - assume tha
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Multi-cycle implementation of the M
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2.5 Draw the functional units neces
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2.9 The instruction, addi (add imme
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Problems with pipelining Hazards Da
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Ex: Represent the 5 stage pipeline
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Example Represent the 5 stage pipel
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Example: Find the size of each pipe
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Pipelined control path - Single cyc
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Control signals with instructions E
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Ex: Show the control signals genera
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Ex: Show the control signals genera
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Lecture 33 Forwarding Unit Design E
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Example: Illustrate the forwarding
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Design a Forwarding unit to integra
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Ex: Forwarding with 2 inst. (1) add
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Lecture 34 Data hazard and stalls F
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Tomasulo • Lasting Contributions
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Tomasulo Organization Page | 217
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4. Show the pipeline execution of f
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7. Illustrate the pipelined data pa
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11. Reorder the following instructi
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15. Design the forwarding unit for
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Temporal locality Low Data Accessin
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Associative mapping More flexible m
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Problems 1. Here is a series of add
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6. What are the miss rate of the fo
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Installation and Usage of Maxplus I
Page 237 and 238:
intend to read registers this instr
Page 239 and 240:
Tomasulo hardware algorithm From Wi
Page 241:
When all operands are available o I
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