Lecture Notes for Computer Architecture II - St. Cloud State University

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4. Using the series of word address references 1, 4, 8, 5, 20, 17, 19, 56, 9, 11 4, 43, 5, 6, 9, 17, show the hits and misses and final cache contents <strong>for</strong> a fully associative cache with one word blocks and a total size of 16 words. Assume LRU replacement. Page | 232 5. Using the series of word address references 1, 4, 8, 5, 20, 17, 19, 56, 9, 11 4, 43, 5, 6, 9, 17, show the hits and misses and final cache contents <strong>for</strong> a fully associative cache with four word blocks and a total size of 16 words. Assume LRU replacement.
6. What are the miss rate of the following code? Consider the direct mapped cache given below to answer this question. Code 1 addi $t0, $0, 5 loop: beq $t0, $0, done lw $t1, 0x4($0) lw $t2, 0xC($0) lw $t3, 0x8($0) addi $t0, $t0, -1 j loop done: Code 2 addi $t0, $0, 5 loop: beq $t0, $0, done lw $t1, 0x4($0) lw $t2, 0xC($0) lw $t3, 0x8($0) lw $t2, 0x24($0) addi $t0, $t0, -1 j loop done: Address 11...11111100 11...11111000 11...11110100 11...11110000 11...11101100 11...11101000 11...11100100 11...11100000 00...00100100 00...00100000 00...00011100 00...00011000 00...00010100 00...00010000 00...00001100 00...00001000 00...00000100 00...00000000 mem[0xFF...FC] mem[0xFF...F8] mem[0xFF...F4] mem[0xFF...F0] mem[0xFF...EC] mem[0xFF...E8] mem[0xFF...E4] mem[0xFF...E0] mem[0x00...24] mem[0x00..20] mem[0x00..1C] mem[0x00...18] mem[0x00...14] mem[0x00...10] mem[0x00...0C] mem[0x00...08] mem[0x00...04] mem[0x00...00] 2 30 Word Main Memory 2 3 Word Cache Set Number 7 (111) 6 (110) 5 (101) 4 (100) 3 (011) 2 (010) 1 (001) 0 (000) Page | 233
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Page | 1 Lecture Notes for Computer
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knowledge given in the book chapter
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CS 320 SCHEDULE (tentative) Week Wh
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6. Project reports - Presentation C
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9. Course policies: 1) Satisfactory
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Size - keep shrinking 1994 124mm 2
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Families of different models - Inte
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Super Computers CRAY - 1 st vector
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Fastest super computers November 20
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Class Activity - 2. Trace the conte
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TUTOR 1.32:> PHYSICAL ADDRESS=00002
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Class Activity 3 - Study of instruc
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Class Activity 4 - Study of instruc
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Performance Improvement at Instruct
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5. Register indirect addressing mod
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High Level Language Statements Ass
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Lecture 7 Data transfer memory reg
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Problem Translate HLL statement A[
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More MIPS instructions jump j jr $S
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Problem Translate the following Whi
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Problem Translate the following exp
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Problem Translate the following exp
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Lecture 10 Translation of High Leve
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Translation of Procedures Problem H
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Example Write the MIPS code to comp
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Program Counter -relative op rs rt
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Example Opcode always 1 byte Memory
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Lecture 13 Enhancing Performance at
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Number Systems Numbers + ve numbers
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Example: Design a one bit ALU with
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Lecture 14 - Performance Improvemen
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Design of Adders c 1 a n , ..., a 1
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Carry lookahead adder Problem with
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Another look at CLA xi + yi = Pi xi
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4-bit CLA Page | 75 generates C3 ge
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Lecture 15 Performance Improvement
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Example 981 X 1234 0981 X 1234 mult
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Example Consider the multiplication
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2 nd version Reduce cost by reducin
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4th step 4 bits registers 0010 4 bi
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0010 ADDER Page | 87 0001 0010 ADDE
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2's complement of m'cand 1111110101
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0010 ADDER Page | 91 1111 0001 1 no
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Lecture 16 - Performance Improvemen
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Hardware units needed to perform th
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Step 1 Rem = Rem - Divisor ( this t
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5th step Rem = Rem - Divisor Now Re
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2nd step Shift remainder left Rem =
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3 rd version of Division algorithm
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Step 3 Rem = Rem - Div Rem > 0 Shif
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Normalized Form keeps one digit lef
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Let us consider the addition of two
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Control path Inputs Exponent differ
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Lecture 19 Architectures for Crypto
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1. Following pseudo code represents
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Find 7 36 mod 11 using right to lef
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Lecture 20 - Performance Chapter -
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total amount of work done in a give
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Question 4 Assuming the CPI for pro
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Question 9 Yet another user has the
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Question 12 Assuming the CPI values
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Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.
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Question 15 We are interested in tw
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Question 18 You are the lead design
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Arithmetic Logic unit Register file
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Lecture 22 - Processor Design - Dat
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Example Design the data path to fet
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Now combine two functional units to
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Lecture 23 Processor Design - Data
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Example : - Design DataPath for SW
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Processor Design - Data path for R&
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Example : - Implement R+ I +J Forma
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31 26 0 4 control signals EX/Addres
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Draw the logic circuit _ _ _ _ _ _
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Single cycle implementation of the
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from Aluop B from output PC Data Ad
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Lecture 27 High level view of the F
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0 Page | 161 1 2 3 5 4 0 - MemRead
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FSM Controller for lw/sw 6 states 0
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Lecture 28 R-type instruction conti
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Branch Instruction Fetch Page | 167
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Jump Inst Fetch Page | 169 Inst dec
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0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
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NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
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Lecture 30 Microprogramming - FSM c
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- Microinstruction placed in a ROM
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Page 189 and 190: Problems with pipelining Hazards Da
Page 191 and 192: Ex: Represent the 5 stage pipeline
Page 193 and 194: Example Represent the 5 stage pipel
Page 195 and 196: Example: Find the size of each pipe
Page 197 and 198: Pipelined control path - Single cyc
Page 199 and 200: Control signals with instructions E
Page 201 and 202: Ex: Show the control signals genera
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Page 205 and 206: Lecture 33 Forwarding Unit Design E
Page 207 and 208: Example: Illustrate the forwarding
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Page 215 and 216: Tomasulo • Lasting Contributions
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Page 219 and 220: 4. Show the pipeline execution of f
Page 221 and 222: 7. Illustrate the pipelined data pa
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Page 225 and 226: 15. Design the forwarding unit for
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Page 229 and 230: Associative mapping More flexible m
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Page 237 and 238: intend to read registers this instr
Page 239 and 240: Tomasulo hardware algorithm From Wi
Page 241: When all operands are available o I
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Lecture Notes for Computer Architecture II - St. Cloud State University

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