Lecture Notes for Computer Architecture II - St. Cloud State University

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Example : Implement R format with I Format instructions lw, sw, add, sub, and - put together all independent data path. - use one clock cycle for all instructions no data path resource is used more than once per inst. memory for instructions memory for data Share many elements in the data path.Use a mux with a data selector. Page | 148 Add +4 PC 15-11 20-16 Aluop 0~31 write data 0~15 25-21 20-16 rr11 rr2 wr wd Sign extension Inst mem Reg file 1 0 mux 32 Read Read Data 2 Data 1 ALUSrc 1 0 Reg write RegDst ALU 0~5 Control 3 Aluop MemWrite MemRead ALU Address Data mem data MemtoRegister 1 0 mux
Example : - Implement R+ I +J Format instructions 1w, sw, beq, add, sub, and - put together all independent data path. - use one clock cycle for all instructions no data path resource is used more than once per inst. memory for instructions memory for data Share many elements in the data path. -Use a mux with a data selector. Page | 149 from sign ext +4 Add PC SL-2 Aluop Read address Add Inst mem 15-11 20-16 Branch 1 0 mux RegDst 0~31 write data 0~15 25-21 20-16 15-11 rr1 rr2 wr wd Sign Reg file Reg write extension 32 Read Read Data 2 Data 1 ALUSrc 1 0 mux ALU Control 3 Aluop ALU MemWrite MemRead Address Data mem data MemtoRegister 1 0 mux
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Page | 1 Lecture Notes for Computer
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knowledge given in the book chapter
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CS 320 SCHEDULE (tentative) Week Wh
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6. Project reports - Presentation C
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9. Course policies: 1) Satisfactory
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Size - keep shrinking 1994 124mm 2
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Families of different models - Inte
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Super Computers CRAY - 1 st vector
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Fastest super computers November 20
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Class Activity - 2. Trace the conte
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TUTOR 1.32:> PHYSICAL ADDRESS=00002
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Class Activity 3 - Study of instruc
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Class Activity 4 - Study of instruc
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Performance Improvement at Instruct
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5. Register indirect addressing mod
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High Level Language Statements Ass
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Lecture 7 Data transfer memory reg
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Problem Translate HLL statement A[
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More MIPS instructions jump j jr $S
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Problem Translate the following Whi
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Problem Translate the following exp
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Problem Translate the following exp
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Lecture 10 Translation of High Leve
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Translation of Procedures Problem H
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Example Write the MIPS code to comp
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Program Counter -relative op rs rt
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Example Opcode always 1 byte Memory
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Lecture 13 Enhancing Performance at
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Number Systems Numbers + ve numbers
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Example: Design a one bit ALU with
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Lecture 14 - Performance Improvemen
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Design of Adders c 1 a n , ..., a 1
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Carry lookahead adder Problem with
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Another look at CLA xi + yi = Pi xi
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4-bit CLA Page | 75 generates C3 ge
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Lecture 15 Performance Improvement
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Example 981 X 1234 0981 X 1234 mult
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Example Consider the multiplication
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2 nd version Reduce cost by reducin
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4th step 4 bits registers 0010 4 bi
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0010 ADDER Page | 87 0001 0010 ADDE
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2's complement of m'cand 1111110101
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0010 ADDER Page | 91 1111 0001 1 no
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Lecture 16 - Performance Improvemen
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Hardware units needed to perform th
Page 97 and 98: Step 1 Rem = Rem - Divisor ( this t
Page 99 and 100: 5th step Rem = Rem - Divisor Now Re
Page 101 and 102: 2nd step Shift remainder left Rem =
Page 103 and 104: 3 rd version of Division algorithm
Page 105 and 106: Step 3 Rem = Rem - Div Rem > 0 Shif
Page 107 and 108: Normalized Form keeps one digit lef
Page 109 and 110: Let us consider the addition of two
Page 111 and 112: Control path Inputs Exponent differ
Page 113 and 114: Lecture 19 Architectures for Crypto
Page 115 and 116: 1. Following pseudo code represents
Page 117 and 118: Find 7 36 mod 11 using right to lef
Page 119 and 120: Lecture 20 - Performance Chapter -
Page 121 and 122: total amount of work done in a give
Page 123 and 124: Question 4 Assuming the CPI for pro
Page 125 and 126: Question 9 Yet another user has the
Page 127 and 128: Question 12 Assuming the CPI values
Page 129 and 130: Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.
Page 131 and 132: Question 15 We are interested in tw
Page 133 and 134: Question 18 You are the lead design
Page 135 and 136: Arithmetic Logic unit Register file
Page 137 and 138: Lecture 22 - Processor Design - Dat
Page 139 and 140: Example Design the data path to fet
Page 141 and 142: Now combine two functional units to
Page 143 and 144: Lecture 23 Processor Design - Data
Page 145 and 146: Example : - Design DataPath for SW
Page 147: Processor Design - Data path for R&
Page 151 and 152: 31 26 0 4 control signals EX/Addres
Page 153 and 154: Draw the logic circuit _ _ _ _ _ _
Page 155 and 156: Single cycle implementation of the
Page 157 and 158: from Aluop B from output PC Data Ad
Page 159 and 160: Lecture 27 High level view of the F
Page 161 and 162: 0 Page | 161 1 2 3 5 4 0 - MemRead
Page 163 and 164: FSM Controller for lw/sw 6 states 0
Page 165 and 166: Lecture 28 R-type instruction conti
Page 167 and 168: Branch Instruction Fetch Page | 167
Page 169 and 170: Jump Inst Fetch Page | 169 Inst dec
Page 171 and 172: Page | 171
Page 173 and 174: 0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
Page 175 and 176: NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
Page 177 and 178: Lecture 30 Microprogramming - FSM c
Page 179 and 180: - Microinstruction placed in a ROM
Page 181 and 182: - In multicycle design - assume tha
Page 183 and 184: Multi-cycle implementation of the M
Page 185 and 186: 2.5 Draw the functional units neces
Page 187 and 188: 2.9 The instruction, addi (add imme
Page 189 and 190: Problems with pipelining Hazards Da
Page 191 and 192: Ex: Represent the 5 stage pipeline
Page 193 and 194: Example Represent the 5 stage pipel
Page 195 and 196: Example: Find the size of each pipe
Page 197 and 198: Pipelined control path - Single cyc
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Control signals with instructions E
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Ex: Show the control signals genera
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Ex: Show the control signals genera
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Lecture 33 Forwarding Unit Design E
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Example: Illustrate the forwarding
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Design a Forwarding unit to integra
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Ex: Forwarding with 2 inst. (1) add
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Lecture 34 Data hazard and stalls F
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Tomasulo • Lasting Contributions
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Tomasulo Organization Page | 217
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4. Show the pipeline execution of f
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7. Illustrate the pipelined data pa
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11. Reorder the following instructi
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15. Design the forwarding unit for
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Temporal locality Low Data Accessin
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Associative mapping More flexible m
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Problems 1. Here is a series of add
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6. What are the miss rate of the fo
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Installation and Usage of Maxplus I
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intend to read registers this instr
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Tomasulo hardware algorithm From Wi
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When all operands are available o I
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Lecture Notes for Computer Architecture II - St. Cloud State University

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