Lecture Notes for Computer Architecture II - St. Cloud State University

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Fastest super computers Fall’07 Rank Site Computer Processors Year R max R peak 1 DOE/NNSA/LLNL United States BlueGene/L - eServer Blue Gene Solution IBM 131072 2005 280600 367000 Page | 16 2 Oak Ridge National Laboratory United States Jaguar - Cray XT4/XT3 Cray Inc. 23016 2006 101700 119350 3 NNSA/Sandia National Laboratories United States Red Storm - Sandia/ Cray Red Storm, Opteron 2.4 GHz dual core Cray Inc. 26544 2006 101400 127411 4 IBM Thomas J. Watson Research Center United States BGW - eServer Blue Gene Solution IBM 40960 2005 91290 114688 5 Stony Brook/BNL, New York Center for Computional Sciences United States New York Blue - eServer Blue Gene Solution IBM 36864 2007 82161 103219 6 DOE/NNSA/LLNL United States ASC Purple - eServer pSeries p5 575 1.9 GHz IBM 12208 2006 75760 92781 7 Rensselaer Polytechnic Institute, Computional Center for Nanotechnology Innovations United States eServer Blue Gene Solution IBM 32768 2007 73032 91750 8 NCSA United States Abe - PowerEdge 1955, 2.33 GHz, Infiniband Dell 9600 2007 62680 89587.2 9 Barcelona Supercomputing Center Spain MareNostrum - BladeCenter JS21 Cluster, PPC 970, 2.3 GHz, Myrinet IBM 10240 2006 62630 94208 10 Leibniz Rechenzentrum Germany HLRB-II - Altix 4700 1.6 GHz SGI 9728 2007 56520 62259.2
Fastest super computers November 2007 http://www.top500.org/ Rank Site Computer Processors Year R max R peak 1 DOE/NNSA/LLNL United States BlueGene/L - eServer Blue Gene Solution IBM Page | 17 212992 2007 478200 596378 2 Forschungszentrum Juelich (FZJ) Germany JUGENE - Blue Gene/P Solution IBM 65536 2007 167300 222822 3 SGI/New Mexico Computing Applications Center (NMCAC) United States SGI Altix ICE 8200, Xeon quad core 3.0 GHz SGI 14336 2007 126900 172032 4 Computational Research Laboratories, TATA SONS India EKA - Cluster Platform 3000 BL460c, Xeon 53xx 3GHz, Infiniband Hewlett-Packard 14240 2007 117900 170880 5 Government Agency Sweden Cluster Platform 3000 BL460c, Xeon 53xx 2.66GHz, Infiniband Hewlett-Packard 13728 2007 102800 146430 6 NNSA/Sandia National Laboratories United States Red Storm - Sandia/ Cray Red Storm, Opteron 2.4 GHz dual core Cray Inc. 26569 2007 102200 127531 7 Oak Ridge National Laboratory United States Jaguar - Cray XT4/XT3 Cray Inc. 23016 2006 101700 119350 8 IBM Thomas J. Watson Research Center United States BGW - eServer Blue Gene Solution IBM 40960 2005 91290 114688 9 NERSC/LBNL United States Franklin - Cray XT4, 2.6 GHz Cray Inc. 19320 2007 85368 100464 10 Stony Brook/BNL, New York Center for Computational Sciences United States New York Blue - eServer Blue Gene Solution IBM 36864 2007 82161 103219
Page 1 and 2: Page | 1 Lecture Notes for Computer
Page 3 and 4: knowledge given in the book chapter
Page 5 and 6: CS 320 SCHEDULE (tentative) Week Wh
Page 7 and 8: 6. Project reports - Presentation C
Page 9 and 10: 9. Course policies: 1) Satisfactory
Page 11 and 12: Size - keep shrinking 1994 124mm 2
Page 13 and 14: Families of different models - Inte
Page 15: Super Computers CRAY - 1 st vector
Page 19 and 20: Class Activity - 2. Trace the conte
Page 21 and 22: TUTOR 1.32:> PHYSICAL ADDRESS=00002
Page 25 and 26: Class Activity 3 - Study of instruc
Page 27 and 28: Class Activity 4 - Study of instruc
Page 33 and 34: Performance Improvement at Instruct
Page 35 and 36: 5. Register indirect addressing mod
Page 37 and 38: High Level Language Statements Ass
Page 39 and 40: Lecture 7 Data transfer memory reg
Page 41 and 42: Problem Translate HLL statement A[
Page 43 and 44: More MIPS instructions jump j jr $S
Page 45 and 46: Problem Translate the following Whi
Page 47 and 48: Problem Translate the following exp
Page 49 and 50: Problem Translate the following exp
Page 51 and 52: Lecture 10 Translation of High Leve
Page 53 and 54: Translation of Procedures Problem H
Page 55 and 56: Example Write the MIPS code to comp
Page 57 and 58: Program Counter -relative op rs rt
Page 59 and 60: Example Opcode always 1 byte Memory
Page 61 and 62: Lecture 13 Enhancing Performance at
Page 63 and 64: Number Systems Numbers + ve numbers
Page 65 and 66: Example: Design a one bit ALU with
Page 67 and 68:
Lecture 14 - Performance Improvemen
Page 69 and 70:
Design of Adders c 1 a n , ..., a 1
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Carry lookahead adder Problem with
Page 73 and 74:
Another look at CLA xi + yi = Pi xi
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4-bit CLA Page | 75 generates C3 ge
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Lecture 15 Performance Improvement
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Example 981 X 1234 0981 X 1234 mult
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Example Consider the multiplication
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2 nd version Reduce cost by reducin
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4th step 4 bits registers 0010 4 bi
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0010 ADDER Page | 87 0001 0010 ADDE
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2's complement of m'cand 1111110101
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0010 ADDER Page | 91 1111 0001 1 no
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Lecture 16 - Performance Improvemen
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Hardware units needed to perform th
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Step 1 Rem = Rem - Divisor ( this t
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5th step Rem = Rem - Divisor Now Re
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2nd step Shift remainder left Rem =
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3 rd version of Division algorithm
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Step 3 Rem = Rem - Div Rem > 0 Shif
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Normalized Form keeps one digit lef
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Let us consider the addition of two
Page 111 and 112:
Control path Inputs Exponent differ
Page 113 and 114:
Lecture 19 Architectures for Crypto
Page 115 and 116:
1. Following pseudo code represents
Page 117 and 118:
Find 7 36 mod 11 using right to lef
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Lecture 20 - Performance Chapter -
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total amount of work done in a give
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Question 4 Assuming the CPI for pro
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Question 9 Yet another user has the
Page 127 and 128:
Question 12 Assuming the CPI values
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Use C2 CPI on M1 = 4*0.3+6*0.2+8*0.
Page 131 and 132:
Question 15 We are interested in tw
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Question 18 You are the lead design
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Arithmetic Logic unit Register file
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Lecture 22 - Processor Design - Dat
Page 139 and 140:
Example Design the data path to fet
Page 141 and 142:
Now combine two functional units to
Page 143 and 144:
Lecture 23 Processor Design - Data
Page 145 and 146:
Example : - Design DataPath for SW
Page 147 and 148:
Processor Design - Data path for R&
Page 149 and 150:
Example : - Implement R+ I +J Forma
Page 151 and 152:
31 26 0 4 control signals EX/Addres
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Draw the logic circuit _ _ _ _ _ _
Page 155 and 156:
Single cycle implementation of the
Page 157 and 158:
from Aluop B from output PC Data Ad
Page 159 and 160:
Lecture 27 High level view of the F
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0 Page | 161 1 2 3 5 4 0 - MemRead
Page 163 and 164:
FSM Controller for lw/sw 6 states 0
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Lecture 28 R-type instruction conti
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Branch Instruction Fetch Page | 167
Page 169 and 170:
Jump Inst Fetch Page | 169 Inst dec
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Page | 171
Page 173 and 174:
0 1 Page | 173 2 6 8 9 3 5 7 4 op 0
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NS0 = 1 + 3 + 5 + 7 + 9 NS1 = 2 + 3
Page 177 and 178:
Lecture 30 Microprogramming - FSM c
Page 179 and 180:
- Microinstruction placed in a ROM
Page 181 and 182:
- In multicycle design - assume tha
Page 183 and 184:
Multi-cycle implementation of the M
Page 185 and 186:
2.5 Draw the functional units neces
Page 187 and 188:
2.9 The instruction, addi (add imme
Page 189 and 190:
Problems with pipelining Hazards Da
Page 191 and 192:
Ex: Represent the 5 stage pipeline
Page 193 and 194:
Example Represent the 5 stage pipel
Page 195 and 196:
Example: Find the size of each pipe
Page 197 and 198:
Pipelined control path - Single cyc
Page 199 and 200:
Control signals with instructions E
Page 201 and 202:
Ex: Show the control signals genera
Page 203 and 204:
Ex: Show the control signals genera
Page 205 and 206:
Lecture 33 Forwarding Unit Design E
Page 207 and 208:
Example: Illustrate the forwarding
Page 209 and 210:
Design a Forwarding unit to integra
Page 211 and 212:
Ex: Forwarding with 2 inst. (1) add
Page 213 and 214:
Lecture 34 Data hazard and stalls F
Page 215 and 216:
Tomasulo • Lasting Contributions
Page 217 and 218:
Tomasulo Organization Page | 217
Page 219 and 220:
4. Show the pipeline execution of f
Page 221 and 222:
7. Illustrate the pipelined data pa
Page 223 and 224:
11. Reorder the following instructi
Page 225 and 226:
15. Design the forwarding unit for
Page 227 and 228:
Temporal locality Low Data Accessin
Page 229 and 230:
Associative mapping More flexible m
Page 231 and 232:
Problems 1. Here is a series of add
Page 233 and 234:
6. What are the miss rate of the fo
Page 235 and 236:
Installation and Usage of Maxplus I
Page 237 and 238:
intend to read registers this instr
Page 239 and 240:
Tomasulo hardware algorithm From Wi
Page 241:
When all operands are available o I
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Lecture Notes for Computer Architecture II - St. Cloud State University

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